PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 310

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Receive Byte Count Low - HDLC Channel 1 (Read)
RBCL
Received Byte Count High - HDLC Channel 1 (Read)
Value after reset: 000
RBCH
OV
RBC(11:8)
Interrupt Status Register 0 (Read)
Value after reset: 00
ISR0
All bits are reset when ISR0 is read.
If bit GCR.VIS is set, interrupt statuses in ISR0 are flagged although they are masked by
register IMR0. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
RME
Data Sheet
RBC7
RME
7
7
7
Together with RBCH, bits RBC(11:8), indicates the length of a
received frame (1 to 4095 bytes). Bits RBC(4:0) indicate the number
of valid bytes currently in RFIFO. These registers must be read by the
CPU following a RME interrupt.
Counter Overflow - HDLC Channel 1
More than 4095 bytes received.
Receive Byte Count - HDLC Channel 1 (most significant bits)
Together with RBCL, bits RBC(7:0) indicates the length of the
received frame.
Receive Message End - HDLC Channel 1
One complete message of length less than 32 bytes, or the last part
of a frame at least 32 bytes long is stored in the receive FIFO,
including the status byte.
RFS
H
xxxxx
T8MS
RMB
OV
310
RBC11
CASC
RBC10
CRC4
SA6SC
RBC9
RBC0
RBC8
FALC56 V1.2
RPF
E1 Registers
0
0
0
PEB 2256
2002-08-27
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