PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 217

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

9.2
Transmit FIFO - HDLC Channel 1 (Write)
XFIFO
XFIFO
Writing data to XFIFO of HDLC channel 1 can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following a XPR
interrupt.
Command Register (Write)
Value after reset: 00
CMDR
RMC
RRES
XREP
Data Sheet
XF15
RMC
XF7
Detailed Description of E1 Control Registers
7
7
Receive Message Complete - HDLC Channel 1
Confirmation from CPU to FALC56 that the current frame or data
block has been fetched following a RPF or RME interrupt, thus the
occupied space in the RFIFO can be released. If RMC is given while
RFIFO is already cleared, the next incoming data block is cleared
instantly, although interrupts are generated.
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one-second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted.
Transmission Repeat - HDLC Channel 1
If XREP is set together with XTF (write 24
repeatedly transmits the contents of the XFIFO (1 to 32 bytes) without
HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with a SRES command or by
resetting XREP.
RRES
Note:During cyclic transmission the XREP-bit has to be set with
H
every write operation to CMDR.
XREP
XRES
217
XHF
XTF
H
XME
to CMDR), the FALC56
SRES
FALC56 V1.2
XF0
XF8
E1 Registers
0
0
PEB 2256
2002-08-27
(00)
(01)
(02)