PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 201

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

8
The three HDLC controllers can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow and the address recognition features can be performed in a very flexible way, to
satisfy almost any practical requirements.
There are 4 different operating modes which can be set via the mode registers (MODE,
MODE2 and MODE3).
If not mentioned otherwise, all functions described for HDLC channel 1 apply to channel
2 and 3 as well.
8.1
All frames with valid addresses are forwarded directly via the RFIFO to the system
memory.
Depending on the selected address mode, the FALC56 can perform a 1- or 2-byte
address recognition (MODE.MDS0).
If a 2-byte address field is selected, the high address byte is compared to the fixed value
FEH or FCH (group address) as well as with two individually programmable values in
RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte
address is interpreted as command/response bit (C/R) and is excluded from the address
comparison.
Similarly, two compare values can be programmed in special registers (RAL1, RAL2) for
the low address byte. A valid address is recognized in case the high and low byte of the
address field correspond to one of the compare values. Thus, the FALC56 can be called
(addressed) with 6 different address combinations. HDLC frames with address fields that
do not match any of the address combinations, are ignored by the FALC56.
In case of a 1-byte address, RAL1 and RAL2 are used as compare registers. The HDLC
control field, data in the I-field and an additional status byte are temporarily stored in the
RFIFO. Additional information can also be read from a special register (RSIS).
As defined by the HDLC protocol, the FALC56 performs the zero bit insertion/deletion
(bit stuffing) in the transmit/receive data stream automatically. That means, it is
guaranteed that at least one “0” will appear after 5 consecutive “1”s.
8.1.1
(MODE.MDS(2:1) = 01; MODE2.MDS22..21=01; MODE3.MDS32..31=01)
Characteristics: address recognition, flag- and CRC generation/check, bit stuffing
All frames with valid addresses are forwarded directly via the RFIFO (RFIFO2, RFIFO3)
to the system memory.
Data Sheet
Signaling Controller Operating Modes
HDLC Mode
Non-Auto Mode
201
Signaling Controller Operating Modes
FALC56 V1.2
PEB 2256
2002-08-27