PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 227

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Interrupt Mask Register 0 to 5 (Read/Write)
Value after reset: FF
IMR0
IMR1
IMR2
IMR3
IMR4
IMR5
IMR(5:0)
Single Bit Defect Insertion Register (Read/Write)
Value after reset: 00
IERR
After setting the corresponding bit, the selected defect is inserted into the transmit data
stream at the next possible position. After defect insertion is completed, the bit is reset
automatically.
IFASE
IMFE
ICRCE
ICASE
IPE
Data Sheet
LLBSC
XPR2
RME
FAR
XSP
ES
7
Interrupt Mask Register
Each interrupt source can generate an interrupt signal on port INT
(characteristics of the output stage are defined by register IPC). A “1”
in a bit position of IMR(5:0) sets the mask active for the interrupt
status in ISR(5:0). Masked interrupt statuses neither generate a
signal on INT, nor are they visible in register GIS. Moreover, they are
- not displayed in the interrupt status register if bit GCR.VIS is cleared
- displayed in the interrupt status register if bit GCR.VIS is set
Note: After reset, all interrupts are disabled.
XPR3
Insert single FAS defect
Insert single multiframe defect
Insert single CRC defect
Insert single CAS defect
Insert single PRBS defect
RDO
RFS
SEC
XSN
LFA
H
H
, FF
H
LMFA16
, FF
IFASE
MFAR
RME2
RME3
T8MS
ALLS
H
, FF
T400MS
H
AIS16
RFS2
RFS3
IMFE
RMB
, FF
XDU
H
227
ICRCE
RDO2
RDO3
CASC
RA16
XMB
AIS
ALLS2
ALLS3
ICASE
CRC4
SUEX
LOS
SA6SC
XDU2
XDU3
XLSC
RAR
RSN
IPE
RPF2
RPF3
FALC56 V1.2
RPF
XPR
RSP
IBV
RA
E1 Registers
0
PEB 2256
2002-08-27
(1B)
(14)
(15)
(16)
(17)
(18)
(19)