C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 12

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
14. Reset Sources....................................................................................................... 163
15. Oscillators ............................................................................................................. 171
16. Flash Memory ....................................................................................................... 177
17. External Data Memory Interface and On-Chip XRAM........................................ 187
18. Port Input/Output.................................................................................................. 203
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Figure 13.17. ACC: Accumulator............................................................................ 150
Figure 13.18. B: B Register .................................................................................... 150
Figure 13.19. IE: Interrupt Enable .......................................................................... 154
Figure 13.20. IP: Interrupt Priority .......................................................................... 155
Figure 13.21. EIE1: Extended Interrupt Enable 1................................................... 156
Figure 13.22. EIE2: Extended Interrupt Enable 2................................................... 157
Figure 13.23. EIP1: Extended Interrupt Priority 1................................................... 158
Figure 13.24. EIP2: Extended Interrupt Priority 2................................................... 159
Figure 13.25. PCON: Power Control ...................................................................... 161
Figure 14.1. Reset Sources.................................................................................... 163
Figure 14.2. Reset Timing ...................................................................................... 164
Figure 14.3. WDTCN: Watchdog Timer Control Register....................................... 167
Figure 14.4. RSTSRC: Reset Source Register ...................................................... 168
Figure 15.1. Oscillator Diagram.............................................................................. 171
Figure 15.2. OSCICL: Internal Oscillator Calibration Register ............................... 172
Figure 15.3. OSCICN: Internal Oscillator Control Register .................................... 172
Figure 15.4. CLKSEL: Oscillator Clock Selection Register .................................... 173
Figure 15.5. OSCXCN: External Oscillator Control Register.................................. 174
Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes ..
Figure 16.2. C8051F066/7 Flash Program Memory Map and Security Bytes ........ 181
Figure 16.3. FLACL: Flash Access Limit ................................................................ 182
Figure 16.4. FLSCL: Flash Memory Control........................................................... 184
Figure 16.5. PSCTL: Program Store Read/Write Control....................................... 185
Figure 17.1. EMI0CN: External Memory Interface Control ..................................... 189
Figure 17.2. EMI0CF: External Memory Configuration........................................... 189
Figure 17.3. Multiplexed Configuration Example.................................................... 190
Figure 17.4. Non-multiplexed Configuration Example ............................................ 191
Figure 17.5. EMIF Operating Modes ...................................................................... 192
Figure 17.6. EMI0TC: External Memory Timing Control......................................... 194
Figure 17.7. Non-multiplexed 16-bit MOVX Timing ................................................ 196
Figure 17.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 197
Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 198
Figure 17.10. Multiplexed 16-bit MOVX Timing...................................................... 199
Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing ....................... 200
Figure 17.12. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 201
Figure 18.1. Port I/O Cell Block Diagram ............................................................... 203
Figure 18.2. Port I/O Functional Block Diagram ..................................................... 204
Figure 18.3. Priority Crossbar Decode Table ......................................................... 205
Figure 18.4. Crossbar Example:............................................................................. 209
180
Rev. 1.2