C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 165

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F060/1/2/3/4/5/6/7
reset until at least 12 clock cycles after the active-low /RST signal is removed. The PINRSF flag (RST-
SRC.0) is set on exit from an external reset.
14.4. Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If
the system clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a
Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset
source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. Setting the
MCDRSF bit, RSTSRC.2 (see Section
“15.
Oscillators” on page 171) enables the Missing Clock Detector.
14.5. Comparator0 Reset
Comparator0 can be configured as a reset input by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled using CPT0CN.7 (see Section
“12.
Comparators” on page 117) prior to
writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The
Comparator0 reset is active-low: if the non-inverting input voltage (CP0+ pin) is less than the inverting
input voltage (CP0- pin), the MCU is put into the reset state. After a Comparator0 Reset, the C0RSEF flag
(RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state
of the /RST pin is unaffected by this reset.
14.6. External CNVSTR2 Pin Reset
The external CNVSTR2 signal can be configured as a reset input by writing a ‘1’ to the CNVRSEF flag
(RSTSRC.6). The CNVSTR2 signal can appear on any of the P0, P1, P2 or P3 I/O pins as described in
Section
“18.1. Ports 0 through 3 and the Priority Crossbar
Decoder” on page 205. Note that the Crossbar
must be configured for the CNVSTR2 signal to be routed to the appropriate Port I/O. The Crossbar should
be configured and enabled before the CNVRSEF is set. CNVSTR2 cannot be used to start ADC2 conver-
sions when it is configured as a reset source. When configured as a reset, CNVSTR2 is active-low and
level sensitive. After a CNVSTR2 reset, the CNVRSEF flag (RSTSRC.6) will read ‘1’ signifying CNVSTR2
as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset.
14.7. Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow
will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application soft-
ware before overflow. If the system experiences a software or hardware malfunction preventing the soft-
ware from restarting the WDT, the WDT will overflow and cause a reset. This should prevent the system
from running out of control.
Following a reset the WDT is automatically enabled and running with the default maximum time interval. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once
locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by
this reset.
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in Figure 14.3.
Rev. 1.2
165

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