C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 318

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F060/1/2/3/4/5/6/7
26.1. Boundary Scan
The DR in the Boundary Scan path is a 126-bit shift register for the
register for the C8051F061/3/5/7. The Boundary DR provides control and observability of all the device
pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands.
318
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
24, 26, 28, 30, 32,
25, 27, 29, 31, 33,
40, 42, 44, 46, 48,
41, 43, 45, 47, 49,
56, 58, 60, 62, 64,
57, 59, 61, 63, 65,
78, 80, 82, 84, 86,
8, 10, 12, 14, 16,
9, 11, 13, 15, 17,
50, 52, 54
51, 53, 55
66, 68, 70
67, 69, 71
72, 74, 76
73, 75, 77
88, 90, 92
18, 20, 22
19, 21, 23
34, 36, 38
35, 37, 39
Bit
0
1
2
3
4
5
6
7
Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6)
Action
Capture Reset Enable from MCU
Update
Capture Reset Input from /RST pin
Update
Capture CAN RX Output Enable to pin
Update
Capture CAN RX Input from pin
Update
Capture CAN TX Output Enable to pin
Update
Capture CAN TX Input from pin
Update
Capture External Clock from XTAL1 pin
Update
Capture Weak Pullup Enable from MCU
Update
Capture P0.n output enable from MCU (e.g. Bit 8 = P0.0, Bit 10 = P0.1, etc.)
Update
Capture P0.n input from pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
Update
Capture P1.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P1.n input from pin (follows P0.n numbering scheme)
Update
Capture P2.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P2.n input from pin (follows P0.n numbering scheme)
Update
Capture P3.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P3.n input from pin (follows P0.n numbering scheme)
Update
Capture P4.5, P4.6, P4.7 (respectively) output enable from MCU
Update
Capture P4.5, P4.6, P4.7 (respectively) input from pin
Update
Capture P5.n output enable from MCU (follows P0.n numbering scheme)
Update
Target
Reset Enable to /RST pin
Not used
CAN RX Output Enable to pin
CAN RX Output to pin
CAN TX Output Enable to pin
CAN TX Output to pin
Not used
Weak Pullup Enable to Port Pins
P0.n output enable to pin (e.g. Bit 8 = P0.0oe, Bit 10 = P0.1oe, etc.)
P0.n output to pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
P1.n output enable to pin (follows P0.n numbering scheme)
P1.n output to pin (follows P0.n numbering scheme)
P2.n output enable to pin (follows P0.n numbering scheme)
P2.n output to pin (follows P0.n numbering scheme)
P3.n output enable to pin (follows P0.n numbering scheme)
P3.n output to pin (follows P0.n numbering scheme)
P4.5, P4.6, P4.7 (respectively) output enable to pin
P4.5, P4.6, P4.7 (respectively) output to pin
P5.n output enable to pin (follows P0.n numbering scheme)
Rev. 1.2
C8051F060/2/4/6
and a 118-bit shift

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