C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 130

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
13.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. There are 256 bytes of internal data
memory and 64 k bytes (C8051F060/1/2/3/4/5) or 32 k bytes (C8051F066/7) of internal program memory
address space implemented within the CIP-51. The CIP-51 memory organization is shown in Figure 13.2.
13.2.1. Program Memory
The CIP-51 has a 64 k byte program memory space. The C8051F060/1/2/3/4/5 devices implement 64 k
bytes of this program memory space as in-system re-programmable Flash memory, organized in a contig-
uous block from addresses 0x0000 to 0xFFFF. Note: 1024 bytes (0xFC00 to 0xFFFF) of this memory are
reserved, and are not available for user program storage. The C8051F066/7 implement 32 k bytes of this
program memory space as in-system re-programmable Flash memory, organized in a contiguous block
from addresses 0x0000 to 0x7FFF.
Program memory is normally assumed to be read-only (using the MOVC instruction). However, the CIP-51
can write to program memory by enabling Flash writes, and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to
130
0x1007F
0x1007F
0x10000
0x10000
0xFBFF
0xFFFF
0xFC00
0xFFFF
0x7FFF
0x0000
0x8000
0x0000
PROGRAM/DATA MEMORY
(In-System Programmable
(In-System Programmable
C8051F060/1/2/3/4/
in 512 Byte Sectors)
in 512 Byte Sectors)
Scrachpad Memory
Scrachpad Memory
C8051F066/7
RESERVED
RESERVED
(data only)
(data only)
(FLASH)
FLASH
FLASH
5
Section “16. Flash Memory” on page 177
0xFF
0x7F
0x2F
0x1F
0x80
0x30
0x20
0x00
Figure 13.2. Memory Map
(Indirect Addressing Only)
(Direct and Indirect
General Purpose
Upper 128 RAM
Bit Addressable
Addressing)
EXTERNAL DATA ADDRESS SPACE
Rev. 1.2
INTERNAL DATA ADDRESS SPACE
Registers
0xFFFF
0x0FFF
0x1000
0x0000
DATA MEMORY (RAM)
XRAM - 4096 Bytes
(accessable using MOVX
(C8051F060/2/4/6 Only)
Off-chip XRAM space
instruction)
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
Special Function
Registers
for further details.
0
256 SFR Pages
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