C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 313

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
Bit7:
Bits6-4:
Bits3-1:
Bit0:
†Note:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
External clock divided by 8 is synchronized with the system clock, and external clock must
be less than or equal to the system clock frequency to operate in this mode.
CPS2
0
0
0
0
1
1
1
1
R/W
Bit6
-
CPS1
0
0
1
1
0
0
1
1
R/W
Bit5
Figure 25.11. PCA0MD: PCA0 Mode Register
-
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8†
Reserved
Reserved
Rev. 1.2
CPS2
R/W
Bit3
C8051F060/1/2/3/4/5/6/7
CPS1
R/W
Bit2
Timebase
CPS0
R/W
Bit1
SFR Address:
SFR Page:
ECF
R/W
Bit0
0xD9
0
Reset Value
00000000
313

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