C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 82
C8051F060DK
Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F060-TB.pdf
(328 pages)
Specifications of C8051F060DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F060/1/2/3/4/5/6/7
82
Bits 7-6: Unused.
Bits 5-0: DMA0 instruction address to write (or read). When DMA0IDT is written or read, this register
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3-0: RESERVED. Write to 0000b.
For more details on DMA instruction words, see
† This register points to a dedicated RAM location and its reset value is indeterminate.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
CCNV
R/W
Bit7
Bit7
R
-
will be incremented to point to the next instruction address.
CCNV: Continuous Conversion.
0: Disable Continuous Conversion.
1: Enable Continuous Conversion. Repeat Counter value is ignored, and conversions will
continue.
DIFFSEL: Wait for data in differential mode.
0: Differential Data will not be collected.
1: Wait for differential data, and store to XRAM.
ADC1EN: Wait for data from ADC1.
0: ADC1 Data will not be collected.
1: Wait for ADC1 data, and store to XRAM.
ADC0EN: Wait for data from ADC0.
0: ADC0 Data will not be collected.
1: Wait for ADC0 data, and store to XRAM. If DIFFSEL is also ‘1’, only the differential data
will be stored.
3
0xDD
3
0xDE
DIFFSEL
R/W
Bit6
Bit6
R
-
Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register
Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register
ADC1EN
R/W
R/W
Bit5
Bit5
ADC0EN
R/W
R/W
Bit4
Bit4
Rev. 1.2
Section “6.2. DMA0 Instruction Format” on page
R/W
R/W
Bit3
Bit3
-
R/W
R/W
Bit2
Bit2
-
R/W
R/W
Bit1
Bit1
-
R/W
R/W
Bit0
Bit0
-
Reset Value†
Reset Value
00000000
xxxxxxxx
76.
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