C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 207

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has
allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected
to SDA, SCL, RX0 (if UART0 is in Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as
Open-Drain outputs, regardless of the settings of the associated bits in the PnMDOUT registers.
18.1.3. Configuring Port Pins as Digital Inputs
A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to
the associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting
P3MDOUT.7 to a logic 0 and P3.7 to a logic 1.
If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input
(for example RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled.
18.1.4. Weak Pull-ups
By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connec-
tion (about 100 k) between the pin and VDD. The weak pull-up devices can be globally disabled by writ-
ing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically
deactivated on any pin that is driving a logic 0; that is, an output pin will not contend with its own pull-up
device. The weak pull-up device can also be explicitly disabled on a Port 1 pin by configuring the pin as an
Analog Input, as described below.
18.1.5. Configuring Port 1 and 2 pins as Analog Inputs
The pins on Port 1 can serve as analog inputs to the ADC2 analog MUX (C8051F060/1/2/3 only) and the
pins on Port 2 can serve as analog inputs to the Comparators (all devices). A Port pin is configured as an
Analog Input by writing a logic 0 to the associated bit in the PnMDIN registers. All Port pins default to a
Digital Input mode. Configuring a Port pin as an analog input:
Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled. Therefore,
the associated PnMDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0
(Open-Drain output mode), and the associated Port Data bits should be set to logic 1 (high-impedance).
Also note that it is not required to configure a Port pin as an Analog Input in order to use it as an input to
ADC2 or the Comparators, however, it is strongly recommended. See the analog peripheral’s correspond-
ing section in this datasheet for further information.
1. Disables the digital input path from the pin. This prevents additional power supply current from
2. Disables the weak pull-up device on the pin.
3. Causes the Crossbar to “skip over” the pin when allocating Port pins for digital peripherals.
being drawn when the voltage at the pin is near VDD / 2. A read of the Port Data bit will return
a logic 0 regardless of the voltage at the Port pin.
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
207

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