C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 304

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F060/1/2/3/4/5/6/7
25.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Read-
ing PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD regis-
ter select the timebase for the counter/timer as shown in Table 25.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 inter-
rupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle
mode.
304
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
CPS2
0
0
0
0
1
1
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
CPS1
C
P
S
2
000
001
010
011
100
101
0
0
1
1
0
0
C
P
S
1
C
P
S
0
E
C
F
CPS0
Figure 25.2. PCA Counter/Timer Block Diagram
IDLE
0
1
0
1
0
1
C
F
Table 25.1. PCA Timebase Input Options
C
R
PCA0CN
C
C
F
5
C
C
F
4
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External oscillator source divided by 8 (synchronized with sys-
tem clock)
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
0
1
Rev. 1.2
PCA0L
read
Snapshot
Register
PCA0H
Timebase
PCA0L
To SFR Bus
To PCA Modules
Overflow
CF
To PCA Interrupt System

Related parts for C8051F060DK