C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 267

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will
typically be required.
22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte:
one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and
received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into
RB80 (SCON0.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop
bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are
met: RI0 must be logic 0, and if SM20 is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
SPACE
MARK
BIT TIMES
BIT SAMPLING
RX (data out)
RX (data in)
TX (clk out)
TX (clk out)
START
BIT
C8051Fxxx
Figure 22.4. UART0 Mode 1 Timing Diagram
D0
Figure 22.3. UART0 Mode 0 Interconnect
Figure 22.2. UART0 Mode 0 Timing Diagram
D0
D1
D0
RX
TX
D1
D1
D2
MODE 0 TRANSMIT
MODE 0 RECEIVE
Rev. 1.2
D2
D2
D3
C8051F060/1/2/3/4/5/6/7
D3
D3
CLK
DATA
D4
D4
8 Extra Outputs
D4
D5
D5
D5
Reg.
Shift
D6
D6
D6
D7
D7
D7
STOP
BIT
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