C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 321

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

26.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all
the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
26.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of
the scan-path latches.
26.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data reg-
ister.
26.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
108, 110, 112, 114,
109, 111, 113, 115,
† Not connected to pins in this device package.
87, 89, 91, 93, 95,
Version = 0000b
Part Number = 0000 0000 0000 0110b (C8051F060/1/2/3/4/5/6/7)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Bit31
102, 104, 106,
103, 105, 107,
97, 99, 101
116
117
Bit
Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7) (Continued)
Version
Bit28 Bit27
Action
Capture P6.n input from pin (follows P0.n numbering scheme)†
Update
Capture P7.n output enable from MCU (follows P0.n numbering scheme)†
Update
Capture P7.n input from pin (follows P0.n numbering scheme)†
Update
Figure 26.2. DEVICEID: JTAG Device ID Register
Part Number
Target
P6.n output to pin (follows P0.n numbering scheme)†
P7.n output enable to pin (follows P0.n numbering scheme)†
P7.n output to pin (follows P0.n numbering scheme)†
Bit12 Bit11
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Manufacturer ID
Bit1
Bit0
1
0xn0006243
Reset Value
321