C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 187

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

17.
The C8051F060/1/2/3/4/5/6/7 MCUs include 4 k bytes of on-chip RAM mapped into the external data
memory space (XRAM). In addition, the C8051F060/2/4/6 include an External Data Memory Interface
which can be used to access off-chip memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) and the
data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction
is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided
by the External Memory Interface Control Register (EMI0CN, shown in Figure 17.1). Note: the MOVX
instruction can also be used for writing to the Flash memory. See
for details. The MOVX instruction accesses XRAM by default.
17.1. Accessing XRAM
The XRAM memory space (both internal and external) is accessed using the MOVX instruction. The
MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses
the Data Pointer, DPTR, a 16-bit register which contains the effective address of the XRAM location to be
read or written. The second method uses R0 or R1 in combination with the EMI0CN register to generate
the effective XRAM address. Examples of both of these methods are given below.
17.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
17.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
External Data Memory Interface and On-Chip XRAM
MOV
MOVX
MOV
MOV
MOVX
DPTR, #1234h
A, @DPTR
EMI0CN, #12h
R0, #34h
a, @R0
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Section “16. Flash Memory” on page 177
187