C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 265

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

22.
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0
may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor commu-
nication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception
of a second incoming data byte before software has finished reading the previous data byte. A Receive
Overrun bit indicates when new received data is latched into the receive buffer before the previously
received byte has been read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The
single SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses
the Receive register and writing SCON0 accesses the Transmit register.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit
Interrupt flag, TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt
flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared
by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by soft-
ware. This allows software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Baud Rate Generation
UART0
F
E
0
R
X
O
V
0
UART0
T
X
C
O
L
0
Logic
SSTA0
M
O
D
S
0
S
0
T
C
L
K
1
C
S
0
T
L
K
1
S
R
C
K
0
L
1
S
0
R
C
L
K
1
Write to
SBUF0
Tx Clock
Rx Clock
Stop Bit
Start
Start
Frame Error
Gen.
Detection
Figure 22.1. UART0 Block Diagram
Load
SBUF0
D
TB80
SET
CLR
Q
Shift
M
S
0
0
SFR Bus
SBUF0
S
M
1
0
Rx Control
Tx Control
M
S
2
0
SCON0
Shift
Input Shift Register
EN
R
N
E
0
Zero Detector
T
B
8
0
SFR Bus
SBUF0
R
B
8
0
(9 bits)
Tx IRQ
T
0
I
SBUF0
Rx IRQ
Rev. 1.2
Read
R
0
I
0x1FF
Match Detect
Address
Match
SBUF
Send
Load
Data
C8051F060/1/2/3/4/5/6/7
TI0
RI0
RB80
SADDR0
SADEN0
RX0
TX0
Crossbar
Crossbar
(UART0) Interrupt
Serial Port
Port I/O
265