C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 204

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
The C8051F06x family of devices have a wide array of digital resources which are available through the
four lower I/O Ports: P0, P1, P2, and (on the C8051F060/2/4/6) P3. Each of the pins on P0, P1, P2, and
P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled by a digital peripheral or
function (like UART0 or /INT1 for example), as shown in Figure 18.2. The system designer controls which
digital functions are assigned pins, limited only by the number of pins available. This resource assignment
flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin
can always be read from its associated Data register regardless of whether that pin has been assigned to
a digital peripheral or behaves as GPIO. The Port pins on Port 2 can be used as analog inputs to the ana-
log Voltage comparators. On the C8051F060/1/2/3, the pins of Port 1 can be used as analog inputs for
ADC2.
The upper Ports (available on C8051F060/2/4/6) can be byte-accessed as GPIO pins, or used as part of
an External Memory Interface which is active during a MOVX instruction whose target address resides in
off-chip memory. See
more information about the External Memory Interface.
204
Highest
Lowest
Priority
Priority
Latches
Port
/SYSCLK
CNVSTR2
T2, T2EX,
T3, T3EX,
T4,T4EX,
Comptr.
Outputs
UART0
UART1
SMBus
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
Section “17. External Data Memory Interface and On-Chip XRAM” on page 187
8
8
8
8
2
4
2
2
6
2
8
Figure 18.2. Port I/O Functional Block Diagram
XBR0, XBR1, XBR2,
P2MDIN, P3MDIN
XBR3 P1MDIN,
Crossbar
Registers
Decoder
Rev. 1.2
Priority
Digital
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Comparators
Registers
ADC2
Input
Cells
Cells
Cells
Cells
To
To
I/O
I/O
I/O
I/O
P0
P1
P2
P3
C8051F060/2
External
Pins
Only
P0.0
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P0.7
Highest
Lowest
Priority
Priority
for