C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 188

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
17.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of four steps:
Each of these four steps is explained in detail in the following sections. The Port enable bit, Multiplexed
mode selection, and Mode bits are located in the EMI0CF register shown in Figure 17.2.
17.3. Port Selection and Configuration
When enabled, the External Memory Interface appears on Ports 7, 6, 5, and 4 in non-multiplexed mode, or
Ports 7, 6, and 4 in multiplexed mode.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches. See
about the Port operation and configuration. The Port latches should be explicitly configured to ‘park’
the External Memory Interface pins in a dormant state when not in use, most commonly by setting
them to a logic 1.
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. See
“18. Port Input/Output” on page 203
188
1. Enable the EMIF on the High Ports (P7, P6, P5, and P4).
2. Configure the Output Modes of the port pins as either push-pull or open-drain (push-pull is
3. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to
4. Select Multiplexed mode or Non-multiplexed mode.
5. Select the memory mode (on-chip only, split mode without bank select, split mode with bank
6. Set up timing to interface with off-chip memory or peripherals.
most common).
logic ‘1’).
select, or off-chip only).
for more information about Port output mode configuration.
Section “18. Port Input/Output” on page 203
Rev. 1.2
for more information
Section