C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 242

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR.
When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if
SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less
than 50 µs (see Figure 20.9, SMBus0 Clock Rate Register).
When the TOE bit in SMB0CN is set to logic 1, Timer 4 is used to detect SCL low timeouts. If Timer 4 is
enabled (see
Section “24.2. Timer 2, Timer 3, and Timer 4” on page
295), Timer 4 is forced to reload when
SCL is high, and forced to count when SCL is low. With Timer 4 enabled and configured to overflow after
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