C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 277

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
23.
UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1).
The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1
accesses the buffered Receive register; writing SBUF1 accesses the Transmit register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive
complete).
Section “23.1. Enhanced Baud Rate Generation” on page
UART1
Rate Generator
UART1 Baud
Write to
SBUF1
Figure 23.1. UART1 Block Diagram
Tx Clock
Rx Clock
Start
Start
Stop Bit
SBUF1
Read
SCON1
TB81
D
SET
CLR
Shift
Input Shift Register
Q
Shift
SFR Bus
(RX Latch)
SBUF1
Rx Control
(9 bits)
Tx Control
0x1FF
SFR Bus
Zero Detector
Rev. 1.2
(TX Shift)
SBUF1
RB81
Load SBUF1
Tx IRQ
Rx IRQ
C8051F060/1/2/3/4/5/6/7
TI1
RI1
SBUF1
Load
Data
Send
278). Received data buffering allows UART1
Interrupt
Serial
Port
RX1
TX1
Crossbar
Crossbar
Port I/O
277

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