C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 312

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
C8051F060/1/2/3/4/5/6/7
25.3. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
312
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
CF
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec-
tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
CCF5: PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
CR
Bit6
CCF5
R/W
Figure 25.10. PCA0CN: PCA Control Register
Bit5
CCF4
R/W
Bit4
Rev. 1.2
CCF3
R/W
Bit3
CCF2
R/W
Bit2
CCF1
R/W
Bit1
SFR Address:
SFR Page:
CCF0
R/W
Bit0
0xD8
0
Reset Value
00000000

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