C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 182

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
ing at 0x0000 up to (but excluding) the FAL address. Software in the upper partition can execute code in
the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc-
tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition
will always return a data value of 0x00.) Software running in the lower partition can access locations in both
the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-
added firmware via the reset vector. Once the value-added firmware completes its initial execution, it
branches to a predetermined location in the upper partition. If entry points are published, software running
in the upper partition may execute program code in the lower partition, but it cannot read the contents of
the lower partition. Parameters may be passed to the program code running in the lower partition either
through the typical method of placing them on the stack or in registers before the call or by placing them in
prescribed memory locations in the upper partition.
The FAL address is specified using the contents of the Flash Access Limit Register. The 16-bit FAL
address is calculated as 0xNN00, where NN is the contents of the FAL Security Register. Thus, the FAL
can be located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase
sector size essentially requires that a 512 boundary be used. The contents of a non-initialized FAL security
byte is 0x00, thereby setting the FAL address to 0x0000 and allowing read access to all locations in pro-
gram memory space by default.
182
Bits 7-0: FLACL: Flash Access Limit.
R/W
Bit7
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This
register can only be written once after any reset. Any subsequent writes are ignored until
the next reset. To fully protect all addresses below this limit, bit 0 of FLACL should be
set to ‘0’ to align the FAL on a 512-byte Flash page boundary.
R/W
Bit6
R/W
Bit5
Figure 16.3. FLACL: Flash Access Limit
R/W
Bit4
Rev. 1.2
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
SFR Page:
R/W
Bit0
0xB7
F
Reset Value
00000000
Address:
SFR