M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet
M-V850E-IA4
Specifications of M-V850E-IA4
Related parts for M-V850E-IA4
M-V850E-IA4 Summary of contents
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... NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com Issued by: Renesas Electronics Corporation (http://www ...
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... Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures ...
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... User’s Manual V850E/IA3, V850E/IA4 32-bit Single-Chip Microcontrollers Hardware V850E/IA3: μ PD703183 μ PD70F3184 V850E/IA4: μ PD703185 μ PD703186 μ PD70F3186 Document No. U16543EJ4V0UD00 (4th edition) Date Published April 2008 N 2003 Printed in Japan ...
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... User’s Manual U16543EJ4V0UD ...
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... Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. ...
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... Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. ...
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... To know the electrical specifications of the V850E/IA3 and V850E/IA4 → The “yyy bit of the xxx register” is described as the “xxx.yyy bit” in this manual. Note with caution that if “xxx.yyy” is described program, however, the compiler/assembler cannot recognize it correctly. The mark <R> shows major revised points. The revised points can be easily searched by copying an “ ...
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... Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary … xxxx or xxxxB Decimal … ...
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... Inverter Control by V850 Series Vector Control by Hole Sensor Application Note Inverter Control by V850 Series Vector Control by Encoder Application Note Inverter Control by V850 Series 120° Excitation Method Control by Zero-Cross Detection Application Note Documents related to development tools (user’s manuals) QB-V850EIA4 (In-circuit emulator) ...
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... Ordering information (V850E/IA4).................................................................................................28 1.3.4 Pin configuration (V850E/IA4).......................................................................................................29 1.3.5 Function blocks (V850E/IA4) ........................................................................................................32 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 35 2.1 List of Pin Functions.................................................................................................................35 2.2 Pin I/O Circuits and Recommended Connection of Unused Pins........................................43 2.3 Pin I/O Circuits...........................................................................................................................46 CHAPTER 3 CPU FUNCTION ................................................................................................................ 47 3.1 Features .....................................................................................................................................47 3.2 CPU Register Set.......................................................................................................................48 3.2.1 Program register set ...
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... Operation .................................................................................................................................194 6.6.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)................................................................ 201 6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001) .................................................... 213 6.6.3 External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010)...................................... 222 6.6.4 One-shot pulse output mode (TPmMD2 to TPmMD0 bits = 011) ............................................... 235 6 ...
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... Interval timer mode (TQnMD2 to TQnMD0 = 000)......................................................................304 7.6.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) ...................................................316 7.6.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .......................................326 7.6.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011).................................................340 7.6.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) ................................................................349 7 ...
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... Stopping conversion operation ................................................................................................... 540 12.9.2 Timer/external trigger interval ..................................................................................................... 540 12.9.3 Operation in standby mode......................................................................................................... 541 12.9.4 Timer interrupt request signal in timer trigger modes 0 and 1..................................................... 542 12.9.5 Re-conversion start trigger input during stabilization time .......................................................... 542 <R> 12.9.6 Variation of A/D conversion results............................................................................................. 542 < ...
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... Writing to the ADA2CTL1 and ADA2CTL3 registers during conversion......................................569 13.7.2 Conflict with timing of storing data in the conversion result register............................................569 CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 571 14.1 Mode Switching Between UARTA1 and CSIB1 ................................................................... 571 14.2 Features .................................................................................................................................. 572 14.3 Configuration.......................................................................................................................... 573 14 ...
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... DMA transfer count registers (DBC0 to DBC3)................................................................. 649 16.3.4 DMA addressing control registers (DADC0 to DADC3) .................................................... 650 16.3.5 DMA channel control registers (DCHC0 to DCHC3)......................................................... 652 16.3.6 DMA trigger factor registers (DTFR0 to DTFR3) .............................................................. 654 16.4 Transfer Modes .......................................................................................................................658 16.4.1 Single transfer mode .................................................................................................................. 658 16 ...
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... Cautions .................................................................................................................................. 737 CHAPTER 22 FLASH MEMORY .......................................................................................................... 738 22.1 Features .................................................................................................................................. 738 22.2 Memory Configuration........................................................................................................... 739 22.3 Functional Overview .............................................................................................................. 740 22.4 Rewriting by Dedicated Flash Memory Programmer ......................................................... 744 22.4.1 Programming environment..........................................................................................................744 22.4.2 Communication mode .................................................................................................................745 22.4.3 Flash memory control .................................................................................................................749 22.4.4 Selection of communication mode ..............................................................................................750 22 ...
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... Features ..................................................................................................................................... 760 22.5.3 Standard self programming flow ................................................................................................. 761 22.5.4 Flash functions ........................................................................................................................... 762 22.5.5 Pin processing ............................................................................................................................ 762 22.5.6 Internal resources used .............................................................................................................. 763 CHAPTER 23 ELECTRICAL SPECIFICATIONS (V850E/IA3)............................................................764 CHAPTER 24 ELECTRICAL SPECIFICATIONS (V850E/IA4)............................................................782 CHAPTER 25 PACKAGE DRAWINGS.................................................................................................801 CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS ...........................................................804 APPENDIX A CAUTIONS ...
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... The V850E/IA3 and V850E/IA4 are 32-bit single-chip microcontrollers that integrate the V850E1 CPU, which is a 32-bit RISC-type CPU core for ASIC, newly developed as the CPU core central to system LSI for the current age of system-on-chip. This device incorporates ROM, RAM, and various peripheral functions such as DMA controller, timer counter, watchdog timer, serial interfaces, an A/D converter, an A/D converter of first-order Δ ...
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... Provided (ports only) External interrupt: 7 (without NMI) Internal interrupt: 48 Timer Q0 Timer Q1 (without output pin) Timer P0 Timer P1 (without output pin) Timer P2 Timer P3 (without output pin) Timer ENC10 TMQ0 + TMQOP0 (+TMP0) Total of two circuits: 6 channels A/D converter 0: 2 channels A/D converter 1: 4 channels ...
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... Features (V850E/IA3) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): CPU features clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock ...
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... M (TMM): 1 channel 16-bit timer/event counter Q (TMQ): 2 channels 16-bit timer/event counter P (TMP): 4 channels Motor control function (uses timer TMQ: 1 channel (TMQ0), TMP: 1 channel (TMP0)) 16-bit accuracy 6-phase PWM function with deadtime: 1 channel High-impedance output control function Timer tuning operation function ...
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... Ordering information (V850E/IA3) Part Number μ PD703183GC-xxx-8BT-A μ PD70F3184GC-8BT-A Remarks 1. xxx indicates ROM code suffix. 2. Products with -A at the end of the part number are lead-free products. 20 CHAPTER 1 INTRODUCTION Package 80-pin plastic QFP (14 × 14) 80-pin plastic QFP (14 × 14) User’s Manual U16543EJ4V0UD ...
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... CMPREF P74/ANI24 12 P75/ANI25 13 ANI10 14 ANI11 15 ANI12 16 ANI13 17 P00/INTP0/TOQ0OFF 18 P02/INTP2/TOP2OFF 19 20 P03/INTP3 μ Notes 1. PD70F3184 only μ 2. PD703183 only CHAPTER 1 INTRODUCTION Top view User’s Manual U16543EJ4V0UD 60 PDL9 59 PDL8 58 PDL7 57 PDL6 Note 1 56 PDL5/FLMD1 55 PDL4 54 PDL3 53 PDL2 PDL1 49 PDL0 48 P37/TCLR10 47 P36/TCUD10 46 P35/TIUD10/TO10 ...
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... Serial output TCLR10: Timer clear TCUD10: Timer control pulse input TIP00, TIP01, TIP20, TIP21, TIQ00 to TIQ03: Timer trigger input TIUD10: Timer count pulse input TO10, TOP00, TOP01, TOP21, TOQ0B1 to TOQ0B3, TOQ0T1 to TOQ0T3, TOQ00 to TOQ03: Timer output 22 CHAPTER 1 INTRODUCTION TOP2OFF, TOQ0OFF: TRGQ0: ...
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... CMPREF AV ADC0 ANI10 to ANI13 Operational amplifier × 3 ADTRG1 Comparator × 3 ADC1 ADC2 ANI20 to ANI25 μ Notes 1. PD703183: 128 KB (mask ROM) μ PD70F3184: 256 KB (flash memory) μ 2. PD703183 μ PD70F3184 μ 3. PD70F3184 only μ 4. PD703183 only CHAPTER 1 INTRODUCTION CPU BCU ROM PC Instruction ...
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... The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. ...
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... Both the ADC0 channels and three of the ADC1 channels include an operation amplifier and a comparator so that these A/D converters can amplify an analog input voltage and detect overvoltage input. (k) ROM correction A ROM correction function that replaces part of a program in the mask ROM or flash memory with a program in the internal RAM is provided four correction addresses can be specified. (l) Ports As shown below, the following ports have general-purpose port functions and control pin functions ...
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... Features (V850E/IA4) Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation) General-purpose registers: 32 bits × 32 Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): CPU features clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock ...
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... A/D converters (A/D converters 0 and 1): 4 channels + 4 channels Three of the four A/D converter channels are provided with an operational amplifier for input level amplification (gain = ×2.5, ×5) and a comparator for overvoltage detection (input voltage range = 0.1AV A/D converter 2, using first-order ΔΣ conversion method: 8 channels ...
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... PD703186GF-xxx-3BA-A μ PD70F3186GC-8EU-A μ PD70F3186GF-3BA-A Remarks 1. xxx indicates ROM code suffix. 2. Products with -A at the end of the part number are lead-free products. 28 CHAPTER 1 INTRODUCTION Package 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × 20) 100-pin plastic LQFP (fine pitch) (14 × 14) 100-pin plastic QFP (14 × ...
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... For the PD703185 and 703186, read as follows. DDO: IC2, DRST: IC3 μ Caution When using the PD703185 or 703186, leave the IC2 and IC3 pins open when they are not used. CHAPTER 1 INTRODUCTION Top view User’s Manual U16543EJ4V0UD 75 PDL9 74 PDL8 ...
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... PD703185 and 703186, read as follows. DDO: IC2, DRST: IC3 μ Caution When using the PD703185 or 703186, leave the IC2 and IC3 pins open when they are not used. 30 CHAPTER 1 INTRODUCTION Top view User’s Manual U16543EJ4V0UD 80 P30/RXDA0 P44/TOP01/TIP01 76 P43/TOP00/TIP00 75 RESET P25/TOQ1B3 69 P24/TOQ1T3 68 P23/TOQ1B2 ...
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... SCKB0, SCKB1: Serial clock SIB0, SIB1: Serial input SOB0, SOB1: Serial output TCLR10, TCLR11: Timer clear TCUD10, TCUD11: Timer control pulse input TIP00, TIP01, TIP20, TIP21, TIQ00 to TIQ03: Timer trigger input TIUD10, TIUD11: Timer count pulse input CHAPTER 1 INTRODUCTION TO10, TO11, ...
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... ANI10 to ANI13 Operational amplifier × 3 ADTRG1 Comparator × 3 ADC2 ANI20 to ANI27 μ Notes 1. PD703185: 128 KB (mask ROM) μ PD703186: 256 KB (mask ROM) μ PD70F3186: 256 KB (flash memory) μ 2. PD703185: μ PD703186, 70F3186 μ 3. PD70F3186 only μ 4. PD703185, 703186 only μ 5. PD70F3186 only μ ...
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... The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (32 bits × 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. ...
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... A/D converters can amplify an analog input voltage and detect overvoltage input. (k) ROM correction A ROM correction function that replaces part of a program in the mask ROM or flash memory with a program in the internal RAM is provided four correction addresses can be specified. (l) On-chip debug function ( An on-chip debug function via an on-chip debug emulator using JTAG interface is provided ...
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... The names and functions of the pins in the V850E/IA3 and V850E/IA4 are listed below. These pins can be divided into port pins and non-port pins according to their function. 2.1 List of Pin Functions There are two power supplies for the I/O buffer of a pin: AV supply and the pins is shown below ...
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... Input data read/output data write is enabled in 1-bit units. An on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected when the pins are in the port mode and input mode, and when TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, and TOP31 pins (output pins of the alternate function) go into a high-impedance state) ...
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... Input data read/output data write is enabled in 1-bit units. An on-chip pull-up resistor can be specified in 1-bit units (the on-chip pull-up resistor can be connected when the pins are in the port mode and input mode, and when the pins function as input pins of the alternate function). Input ...
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... I/O port PDL1 Input data read/output data write is enabled in 1-bit units. PDL2 on-chip pull-up resistor can be specified in 1-bit units PDL3 (the on-chip pull-up resistor can be connected only when the pins are in the port mode and input mode). PDL4 PDL5 PDL6 PDL7 58 71 ...
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... DD Note 2 Note 2 Note 2 supply pin) − AV Ground potential for A/D converters Note 3 Note 3 Note 3 − CMPREF Comparator reference power supply for A/D converters 0, 1 − Power supply for oscillator and PLL (2.5 V power supply pin) DD − Ground potential for oscillator and PLL SS Notes 1 ...
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... Debug clock input for on-chip debug emulator − Note 1 DDI 82 10 Input Debug data input for on-chip debug emulator − Note 1 DDO 98 26 Output Debug data output for on-chip debug emulator − Note 1 DMS 84 12 Input Debug mode select for on-chip debug emulator − Note 1 DRST 99 ...
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... Pin Name Pin No. I/O IA3 IA4 PLLSIN 80 100 28 Input Output frequency select signal input in PLL mode RESET Input System reset input RXDA0 Input Serial receive data input of UARTA0, UARTA1 RXDA1 SCKB0 I/O Serial clock I/O of CSIB0, CSIB1 SCKB1 SIB0 Input Serial receive data input of CSIB0, CSIB1 ...
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... Note 1 TOQ1T3 41 69 TRGQ0 Input External trigger input of TMQ0 TXDA0 Output Serial transmit data output of UARTA0, UARTA1 TXDA1 − V Positive power supply for internal unit (2.5 V power supply pin) DD Note 2 Note 2 Note 2 − V Ground potential for internal unit SS Note 3 Note 3 Note 3 ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins It is recommended that kΩ resistors be used when connecting to EV Pin Name Alternate-Function Pin Name P00 INTP0/TOQ0OFF Note Note Note P01 INTP1 /TOQ1OFF P02 INTP2/TOP2OFF Note P03 INTP3/TOP3OFF P04 INTP4/ADTRG0 P05 INTP5/ADTRG1 P06 ...
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... I/O Circuit Type IA3 IA4 5-AH Input 5-AG Output: Leave open 5- − Note − − Connect − − 5-AG Input Output: Leave open μ PD70F3186 (V850E/IA4) only User’s Manual U16543EJ4V0UD (2/3) Recommended Connection Independently connect via a resistor Independently connect via a resistor. ...
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... PD70F3186 (V850E/IA4) only μ 3. PD70F3184 (V850E/IA3), μ 4. PD703183 (V850E/IA3), Remarks 1. IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × 14) GF (V850E/IA4): 100-pin plastic QFP (14 × 20 CHAPTER 2 PIN FUNCTIONS Pin No. I/O Circuit Type ...
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... Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 2 Type 3-C EV Data EV Type 5-AG Pullup enable EV Data Output disable Input enable 46 CHAPTER 2 PIN FUNCTIONS Type 5-AH Pullup enable Data Output disable Input enable Type 7 P-ch IN N-ch AV Type 7-C ...
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... The CPU of the V850E/IA3 and V850E/IA4 are based on RISC architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 Features Minimum instruction execution time: 15 MHz internal operation) Thirty-two 32-bit general-purpose registers Internal 32-bit architecture Five-stage pipeline control ...
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... CPU Register Set The registers of the V850E/IA3 and V850E/IA4 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have a 32-bit width. For details, refer to V850E1 Architecture User’s Manual. (1) Program register set ...
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... C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost. The contents must be restored to the registers after the registers have been used. r2 may be used by the real-time OS. If the real-time OS does not use r2, it can be used as a variable register. ...
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... Reserved for future function expansion (operations that access these register numbers cannot be guaranteed). Notes 1. Because this register has only one set, to enable multiple interrupts necessary to save this register by program. 2. Can be accessed only after the DBTRAP instruction or illegal opcode is executed and before the < ...
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... Acknowledge Interrupts). The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits EIPC and bits EIPSW are reserved (fixed to 0) for future function expansion. ...
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... NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. ...
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... SAT Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed ...
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... CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. ...
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... Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. ...
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... In this mode, execution branches to the reset entry address in the internal ROM and instruction processing is started when system reset is released. (2) Flash memory programming mode ( If this mode is specified, a program can be written to the internal flash memory by the flash memory programmer. 3.3.2 Operating mode specification The operating mode is specified according to the status of the FLMD0 and FLMD1 pins ...
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... CPU address space The CPU of the V850E/IA3 and V850E/IA4 has 32-bit architecture and supports linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum linear address space (program space) is supported. Figure 3-2 shows the CPU address space. ...
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... Image A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits the CPU address. Figure 3-3 shows the image of the virtual addressing space. Physical address x0000000H can be seen as CPU address 00000000H, and in addition, can be seen as address 10000000H, address 20000000H, … ...
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... Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit result of a branch address calculation, the higher 6 bits ignore the carry or borrow. ...
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... I/O area Internal RAM area Access prohibited Internal ROM area CHAPTER 3 CPU FUNCTION Figure 3-4. Memory Map μ PD703183 (V850E/IA3) μ PD703185 (V850E/IA4) On-chip peripheral I/O area Internal RAM area Access prohibited Internal ROM area User’s Manual U16543EJ4V0UD 256 256 KB 128 KB ...
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... MB of internal ROM area, addresses 00000H to FFFFFH, is reserved. μ (a) PD703183 (V850E/IA3), 128 KB are provided at addresses 000000H to 01FFFFH as physical internal ROM. μ (b) PD70F3184 (V850E/IA3), 256 KB are provided at addresses 000000H to 03FFFFH as physical internal ROM. CHAPTER 3 CPU FUNCTION μ PD703185 (V850E/IA4) Figure 3-5. Internal ROM Area (128 KB Access prohibited area ...
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... Internal RAM area The 12 KB area of addresses FFFC000H to FFFEFFFH is reserved for the internal RAM area. μ (a) PD703183 (V850E/IA3), The 6 KB area of addresses FFFD800H to FFFEFFFH is provided as physical internal RAM. Caution The following areas are access-prohibited. Addresses FFFC000H to FFFD7FFH μ (b) PD70F3184 (V850E/IA3), The 12 KB area of addresses FFFC000H to FFFEFFFH is provided as physical internal RAM. ...
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... VSWC register and “0x01” of instruction <4> is the set value of the IMS register. Be sure to set a value to the IMS register in accordance with the internal RAM size to be set (see Caution 2). [Description example] < ...
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... KB (FFFD800H to FFFEFFFH (FFFC000H to FFFEFFFH) (3) On-chip peripheral I/O area memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH Note Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. ...
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... Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Therefore, a contiguous 64 MB space, starting from address 00000000H, unconditionally corresponds to the memory map of the program space. ...
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... Notes 1. This area is access-prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. 2. The operation is not guaranteed if an access-prohibited area is accessed. Remarks 1. The arrows indicate the recommended area. 2. This is a recommended memory map when the operation mode. 66 CHAPTER 3 CPU FUNCTION Data space ...
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... DMA source address register 3L FFFFF09AH DMA source address register 3H FFFFF09CH DMA destination address register 3L FFFFF09EH DMA destination address register 3H FFFFF0C0H DMA transfer count register 0 FFFFF0C2H DMA transfer count register 1 FFFFF0C4H DMA transfer count register 2 FFFFF0C6H DMA transfer count register 3 FFFFF0D0H DMA addressing control register 0 ...
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... Function Register Name FFFFF104H Interrupt mask register 2 FFFFF104H Interrupt mask register 2L FFFFF105H Interrupt mask register 2H FFFFF106H Interrupt mask register 3 FFFFF106H Interrupt mask register 3L FFFFF107H Interrupt mask register 3H FFFFF110H Interrupt control register FFFFF112H Interrupt control register FFFFF114H Interrupt control register FFFFF116H Interrupt control register ...
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... Power save control register FFFFF200H A/D converter 0 mode register 0 FFFFF201H A/D converter 0 mode register 1 FFFFF202H A/D converter 0 channel specification register FFFFF203H A/D converter 0 mode register 2 FFFFF210H A/D0 conversion result register 0 FFFFF211H A/D0 conversion result register 0H FFFFF212H A/D0 conversion result register 1 FFFFF213H ...
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... A/D0 conversion result register 6H FFFFF21EH A/D0 conversion result register 7 FFFFF21FH A/D0 conversion result register 7H FFFFF220H A/D converter 1 mode register 0 FFFFF221H A/D converter 1 mode register 1 FFFFF222H A/D converter 1 channel specification register FFFFF223H A/D converter 1 mode register 2 FFFFF230H A/D1 conversion result register 0 FFFFF231H ...
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... Address Function Register Name FFFFF260H Operational amplifier 0 control register 0 FFFFF261H Operational amplifier 0 control register 1 FFFFF268H Operational amplifier 1 control register 0 FFFFF269H Operational amplifier 1 control register 1 FFFFF310H External interrupt noise elimination control register FFFFF400H Port 0 register FFFFF402H Port 1 register FFFFF404H Port 2 register FFFFF406H ...
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... Address Function Register Name FFFFF596H CC101 capture input select register FFFFF598H Noise elimination time select register 10 FFFFF5A0H Timer ENC11 FFFFF5A2H Compare register 110 FFFFF5A4H Compare register 111 FFFFF5A6H Capture/compare register 110 FFFFF5A8H Capture/compare register 111 FFFFF5AAH Capture/compare control register 11 FFFFF5ABH Timer unit mode register 11 ...
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... FFFFF668H TMP1 capture/compare register 1 FFFFF66AH TMP1 counter read buffer register FFFFF680H TMP2 control register 0 FFFFF681H TMP2 control register 1 FFFFF682H TMP2 I/O control register 0 FFFFF683H TMP2 I/O control register 1 FFFFF684H TMP2 I/O control register 2 FFFFF685H TMP2 option register 0 FFFFF686H TMP2 capture/compare register 0 ...
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... Port 1 function control expansion register FFFFF802H System status register FFFFF810H DMA trigger factor register 0 FFFFF812H DMA trigger factor register 1 FFFFF814H DMA trigger factor register 2 FFFFF816H DMA trigger factor register 3 FFFFF820H Power save mode register FFFFF828H Processor clock control register FFFFF82CH PLL control register ...
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... FFFFFD03H CSIB0 status register FFFFFD04H CSIB0 receive data register FFFFFD04H CSIB0 receive data register L FFFFFD06H CSIB0 transmit data register FFFFFD06H CSIB0 transmit data register L FFFFFD10H CSIB1 control register 0 FFFFFD11H CSIB1 control register 1 FFFFFD12H CSIB1 control register 2 FFFFFD13H CSIB1 status register FFFFFD14H ...
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... In addition, a command register (PRCDM) is provided to protect against a write access to the special registers so that the application system does not inadvertently stop due to a program hang-up. A write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the system status register (SYS). 76 CHAPTER 3 CPU FUNCTION User’ ...
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... Note Five NOP instructions or more must be inserted immediately after setting the IDLE mode or STOP mode (by setting the PSC.STB bit to 1). Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not acknowledged. This is because it is assumed that steps <2> and <3> above are performed by successive store instructions. If another instruction is placed between < ...
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... The first write access to a special register is valid after data has been written in advance to the PRCMD register. In this way, the value of the special register can be rewritten only in a specific sequence protect the register from an illegal write access ...
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... Status flags that indicate the operation status of the overall system are allocated to this register. If this register is not written in the correct sequence including an access to the PRCMD register, data is not written to the intended register, a protection error occurs, and the PRERR flag is set. This register is cleared by writing “ ...
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... Consequently, access to the on-chip peripheral I/O register may take a long time. 3.4.10 Cautions Use the processing in either (1) or (2) below to set the internal RAM size the μ and PD70F3186 (V850E/IA4). ...
Page 83
... Input and output can be specified in 1-bit units. On-chip pull-up resistor can be connected in 1-bit units (ports and DL only) However, an on-chip pull-up resistor can only be connected when the pins are in input mode in the port mode, or when the pins function as input pins in the alternate-function mode. Moreover, an on-chip pull-up resistor can be ...
Page 84
... P00, P02 to P07, P10 to P17, P30 to P37, P40 to P44, PDL0 to PDL15, DD RESET 82 CHAPTER 4 PORT FUNCTIONS and EV . The relationship between each of these DD DD P00 P40 P02 P44 P07 P70 P10 P75 P17 P30 PDL0 P37 PDL15 Corresponding Pins User’s Manual U16543EJ4V0UD Port 4 Port 7 Port DL ...
Page 85
... The relationship between each of these DD DD P00 P40 P44 P07 P50 P10 P17 P52 P20 P70 P27 P77 P30 PDL0 PDL15 P37 Corresponding Pins Note Note Note , DMS , DDI , DDO User’s Manual U16543EJ4V0UD Port 4 Port 5 Port 7 Port DL Note Note , DRST 83 ...
Page 86
... Port Configuration Table 4-3. Port Configuration (V850E/IA3) Item Control registers Port n register (Pn DL) Port n mode register (PMn DL) Port n mode control register (PMCn Port n function control register (PFCn Port 1 function control expansion register (PFCE1) Pull-up resistor option register (PUn DL) Ports Input-only: 6, I/O: 44 ...
Page 87
... Also, the value of the Pn register is read when the PMn register is in the output mode while the alternate function is set the PMn register is in the input mode while the alternate function is set, the statuses of the pins at that time are read regardless of whether the alternate function is an input or output function. ...
Page 88
... Output mode 1 Input mode (3) Port n mode control register (PMCn) The PMCn register specifies the port mode or alternate function. Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. After reset: 00H PMCn PMCn7 PMCn6 ...
Page 89
... Port n function control expansion register (PFCEn) The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units ...
Page 90
... INTR0.INTR0n bit = 0), select external interrupt input (INTPn), and then specify the valid edge ( 7). When switching to the port mode from external interrupt input (INTPn) (PMC0n bit = 1 → 0), an edge may be detected. Be sure to disable edge detection (INTF0n bit = 0, INTR0n bit = 0), and then select the port mode. Remark Switch to the alternate function using the following procedure. < ...
Page 91
... CHAPTER 10 CONTROL FUNCTION) and A/D converters 0 and 1 (see CHAPTER 12 A/D CONVERTERS 0 AND 1) after noise is eliminated by a port (analog delay). In addition, a signal whose edge was detected is input to the interrupt controller (INTC) as INTPn (V850E/IA3 V850E/IA4 5). Edge detection is performed by the high-impedance output controller and A/D converters 0 and 1 ...
Page 92
... P06 (specified by INTPNRC register) PMC06 bit P07 PMC07 bit Caution To control high-impedance output of the external interrupt function and motor output control function, set the PMC0a bit to 1 (V850E/IA3 V850E/IA4 7). Remark only in PMC0n bit) (V850E/IA3 (V850E/IA4 CHAPTER 4 PORT FUNCTIONS Noise Edge ...
Page 93
... With the V850E/IA3, be sure to set this bit to 1. Remark V850E/IA3 V850E/IA4 CHAPTER 4 PORT FUNCTIONS R/W Address: FFFFF400H P05 P04 P03 P02 Control of output data (in output mode) Address: FFFFF420H PM05 PM04 PM03 PM02 Control of input/output mode (in port mode) User’s Manual U16543EJ4V0UD Note P01 ...
Page 94
... PMC05 PMC04 PMC03 PMC02 PMC01 Specification of operating mode of P07 pin Specification of operating mode of P06 pin Specification of operating mode of P05 pin Specification of operating mode of P04 pin Specification of operating mode of P03 pin Note 2 input Specification of operating mode of P02 pin Specification of operating mode of P01 pin Specification of operating mode of P00 pin User’ ...
Page 95
... Connect Notes 1. Valid only in the V850E/IA4. With the V850E/IA3, be sure to clear this bit on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as alternate-function pins. connected when the pins are in output mode. ...
Page 96
... Block diagram Figure 4-4. Block Diagram of P00 to P05 and P07 Pins WR PU PU0 PU0n WR INTR INTR0 INTR0n WR INTF INTF0 INTF0n WR PMC PMC0 PMC0n WR PM PM0 PM0n WR PORT P0 P0n Address RD INTP0, INTP2 to INTP5 input, Noise elimination Note INTP7, INPT1 input Edge detection ...
Page 97
... CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P06 Pin WR PU PU0 PU06 WR INTR INTR0 INTR06 WR INTF INTF0 INTF06 WR PMC PMC0 PMC06 WR PM PM0 PM06 WR PORT P0 P06 Address RD Noise elimination INTP6 input Edge detection User’s Manual U16543EJ4V0UD P-ch Digital noise elimination ...
Page 98
... Port 1 Port 1 can be set to the input or output mode in 1-bit units. Port 1 has an alternate function as the following pins. Table 4-7. Alternate-Function Pins of Port 1 Port Pin No. IA3 IA4 P10 P11 P12 P13 P14 P15 P16 P17 Note Software pull-up function Caution When P10 to P15 and P17 are used as TOQ0T1 to TOQ0T3, TOQ0B1 to TOQ0B3, and TOP21, output is stopped when the following signals are asserted. • ...
Page 99
... PM16 PM1n 0 Output mode 1 Input mode Remark CHAPTER 4 PORT FUNCTIONS R/W Address: FFFFF402H P15 P14 P13 P12 Control of output data (in output mode) Address: FFFFF422H PM15 PM14 PM13 PM12 Control of input/output mode (in port mode) User’s Manual U16543EJ4V0UD P11 P10 PM11 PM10 97 ...
Page 100
... PMC14 PMC13 PMC12 Specification of operating mode of P17 pin Specification of operating mode of P16 pin Specification of operating mode of P15 pin Specification of operating mode of P14 pin Specification of operating mode of P13 pin Specification of operating mode of P12 pin Specification of operating mode of P11 pin Specification of operating mode of P10 pin User’ ...
Page 101
... Port 1 function control function expansion register (PFCE1) After reset: 00H R/W PFCE1 0 0 Remark For the specification of alternate function, see 4.3.2 (1) (f) Setting of alternate function of port 1. CHAPTER 4 PORT FUNCTIONS Address: FFFFF462H PFC15 PFC14 PFC13 PFC12 Address: FFFFF702H PFCE12 PFCE11 User’s Manual U16543EJ4V0UD PFC11 PFC10 PFCE10 99 ...
Page 102
... Specification of Alternate Function of P12 Pin TOQ0T2 output TIQ03 input TOQ03 output Setting prohibited Specification of Alternate Function of P11 Pin TOQ0B1 output TIQ02 input TOQ02 output Setting prohibited Specification of Alternate Function of P10 Pin TOQ0T1 output TIQ01 input TOQ01 output Setting prohibited User’s Manual U16543EJ4V0UD ...
Page 103
... Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode. Moreover, an on-chip pull-up resistor can be connected to the TOQ0T1 to TOQ0T3, TOQ0B1 to TOQ0B3, and TOP21 pins, these are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the TOQ0OFF or TOP2OFF pin, or software processing ...
Page 104
... TOQ0T2 output TOQ01 to TOQ03 output WR PORT P1 P1n Address RD TIQ01 to TIQ03 input Notes 1. Output of high impedance setting signal from high impedance output controller 2. Output of clock stop detection signal from clock monitor Remark 102 CHAPTER 4 PORT FUNCTIONS Digital noise elimination User’s Manual U16543EJ4V0UD ...
Page 105
... TOQ0B3, TOP21 output WR PORT P1 P1n Address RD TIQ00, EVTQ0, TRGQ0, TIP21 input Notes 1. Output of high impedance setting signal from high impedance output controller 2. Output of clock stop detection signal from clock monitor Remark CHAPTER 4 PORT FUNCTIONS Digital noise elimination User’s Manual U16543EJ4V0UD ...
Page 106
... WR PU PU1 PU16 WR PFC PFC1 PFC16 WR PMC PMC1 PMC16 WR PM PM1 PM16 TOQ00 output WR PORT P1 P16 Address RD TIP20 input 104 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P16 Pin Digital noise elimination User’s Manual U16543EJ4V0UD P-ch P16/TOQ00/TIP20 ...
Page 107
... Port 2 (V850E/IA4 only) Port 2 can be set to the input or output mode in 1-bit units. Port 2 has an alternate function as the following pins. Table 4-8. Alternate-Function Pins of Port 2 Port Pin No P20 35 63 P21 36 64 P22 37 65 P23 40 68 P24 41 69 P25 42 70 P26 60 88 ...
Page 108
... PM2n 0 Output mode 1 Input mode Remark 106 CHAPTER 4 PORT FUNCTIONS R/W Address: FFFFF404H P25 P24 P23 P22 Control of output data (in output mode) Address: FFFFF424H PM25 PM24 PM23 PM22 Control of input/output mode (in port mode) User’s Manual U16543EJ4V0UD P21 P20 PM21 PM20 ...
Page 109
... PMC24 PMC23 PMC22 Specification of operating mode of P27 pin Specification of operating mode of P26 pin Specification of operating mode of P25 pin Specification of operating mode of P24 pin Specification of operating mode of P23 pin Specification of operating mode of P22 pin Specification of operating mode of P21 pin Specification of operating mode of P20 pin User’ ...
Page 110
... Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode. Moreover, an on-chip pull-up resistor can only be connected to the TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, and TOP31 pins, these pins are output pins in the alternate-function mode, when these pins go into a high-impedance state due to the TOQ1OFF or TOP3OFF pin, or software processing ...
Page 111
... PM2n TOQ1T1 to TOQ1T3, TOQ1B1 to TOQ1B3, TOP31 output WR PORT P2 P2n Address RD Notes 1. Output of high impedance setting signal from high impedance output controller 2. Output of clock stop detection signal from clock monitor Remark CHAPTER 4 PORT FUNCTIONS User’s Manual U16543EJ4V0UD P-ch P20/TOQ1T1 P21/TOQ1B1 P22/TOQ1T2 ...
Page 112
... WR PU PU2 PU26 WR PMC PMC2 PMC26 WR PM PM2 PM26 TOQ10 output WR PORT P2 P26 Address RD 110 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P26 Pin User’s Manual U16543EJ4V0UD P-ch P26/TOQ10 ...
Page 113
... Port 3 Port 3 can be set to the input or output mode in 1-bit units. Port 3 has an alternate function as the following pins. Table 4-9. Alternate-Function Pins of Port 3 Port Pin No. IA3 IA4 P30 P31 P32 P33 P34 P35 P36 P37 Note Software pull-up function Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × ...
Page 114
... PM3n 0 Output mode 1 Input mode Remark 112 CHAPTER 4 PORT FUNCTIONS R/W Address: FFFFF406H P35 P34 P33 P32 Control of output data (in output mode) Address: FFFFF426H PM35 PM34 PM33 PM32 Control of input/output mode (in port mode) User’s Manual U16543EJ4V0UD P31 P30 PM31 PM30 ...
Page 115
... PMC34 PMC33 PMC32 Specification of operating mode of P37 pin Specification of operating mode of P36 pin Specification of operating mode of P35 pin Specification of operating mode of P34 pin Specification of operating mode of P33 pin Specification of operating mode of P32 pin Specification of operating mode of P31 pin Specification of operating mode of P30 pin User’ ...
Page 116
... PU3n 0 1 Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or <R> when the pins function as input pins in the alternate-function mode (including the slave mode of the SCKB1 pin). An on-chip pull-up resistor cannot be connected when the pins are in output mode. ...
Page 117
... Block diagram Figure 4-11. Block Diagram of P30 Pin WR PU PU3 PU30 WR PMC PMC3 PMC30 WR PM PM3 PM30 WR PORT P3 P30 Address RD RXDA0 input CHAPTER 4 PORT FUNCTIONS User’s Manual U16543EJ4V0UD P-ch P30/RXDA0 115 ...
Page 118
... WR PU PU3 PU31 WR PMC PMC3 PMC31 WR PM PM3 PM31 TXDA0 output WR PORT P3 P31 Address RD 116 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 Pin User’s Manual U16543EJ4V0UD P-ch P31/TXDA0 ...
Page 119
... CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P32 Pin WR PU PU3 PU32 WR PFC PFC3 PFC32 WR PMC PMC3 PMC32 WR PM PM3 PM32 WR PORT P3 P32 Address RD SIB1 input RXDA1 input User’s Manual U16543EJ4V0UD P-ch P32/SIB1/RXDA1 117 ...
Page 120
... WR PU PU3 PU33 WR PFC PFC3 PFC33 WR PMC PMC3 PMC33 WR PM PM3 PM33 SOB1 output TXDA1 output WR PORT P3 P33 Address RD 118 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P33 Pin User’s Manual U16543EJ4V0UD P-ch P33/SOB1/TXDA1 ...
Page 121
... CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P34 Pin WR PU PU3 PU34 SCKB1 master mode WR PMC PMC3 PMC34 WR PM PM3 PM34 SCKB1 output WR PORT P3 P34 Address RD SCKB1 input User’s Manual U16543EJ4V0UD P-ch P34/SCKB1 119 ...
Page 122
... WR PU PU3 PU35 WR PFC PFC3 PFC35 WR PMC PMC3 PMC35 WR PM PM3 PM35 TO10 output WR PORT P3 P35 Address RD TIUD10 input 120 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P35 Pin Digital noise elimination User’s Manual U16543EJ4V0UD P-ch P35/TIUD10/TO10 ...
Page 123
... Figure 4-17. Block Diagram of P36 and P37 Pins WR PU PU3 PU3n WR PMC PMC3 PMC3n WR PM PM3 PM3n WR PORT P3 P3n Address RD TCUD10, TCLR10 input Remark CHAPTER 4 PORT FUNCTIONS Digital noise elimination User’s Manual U16543EJ4V0UD P-ch P36/TCUD10 P37/TCLR10 121 ...
Page 124
... Port 4 Port 4 can be set to the input or output mode in 1-bit units. Port 4 has an alternate function as the following pins. Table 4-10. Alternate-Function Pins of Port 4 Port Pin No. IA3 IA4 P40 P41 P42 P43 P44 Note Software pull-up function Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × ...
Page 125
... Port 4 mode register (PM4) After reset: FFH R/W PM4 1 1 PM4n 0 Output mode 1 Input mode Remark (c) Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 0 PMC44 0 I/O port 1 TOP01 output/TIP01 input PMC43 0 I/O port 1 TOP00 output/TIP00 input PMC42 0 I/O port ...
Page 126
... Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode (including when in the SCKB0 pin slave mode). An on-chip pull-up resistor cannot be connected when the pins are in output mode. ...
Page 127
... Block diagram Figure 4-18. Block Diagram of P40 Pin WR PU PU4 PU40 WR PMC PMC4 PMC40 WR PM PM4 PM40 WR PORT P4 P40 Address RD SIB0 input CHAPTER 4 PORT FUNCTIONS User’s Manual U16543EJ4V0UD P-ch P40/SIB0 125 ...
Page 128
... WR PU PU4 PU41 WR PMC PMC4 PMC41 WR PM PM4 PM41 SOB0 output WR PORT P4 P41 Address RD 126 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P41 Pin User’s Manual U16543EJ4V0UD P-ch P41/SOB0 ...
Page 129
... CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P42 Pin WR PU PU4 PU42 SCKB0 master mode WR PMC PMC4 PMC42 WR PM PM4 PM42 SCKB0 output WR PORT P4 P42 Address RD SCKB0 input User’s Manual U16543EJ4V0UD P-ch P42/SCKB0 127 ...
Page 130
... Figure 4-21. Block Diagram of P43 and P44 Pins WR PU PU4 PU4n WR PFC PFC4 PFC4n WR PMC PMC4 PMC4n WR PM PM4 PM4n TOP00, TOP01 output WR PORT P4 P4n Address RD TIP00, TIP01 input Remark 128 CHAPTER 4 PORT FUNCTIONS Digital noise elimination User’s Manual U16543EJ4V0UD ...
Page 131
... Port 5 (V850E/IA4 only) Port 5 can be set to the input or output mode in 1-bit units. Port 5 has an alternate function as the following pins. Table 4-11. Alternate-Function Pins of Port 5 Port Pin No P50 82 10 P51 83 11 P52 84 12 Notes 1. Software pull-up function μ 2 PD70F3186 only 3. The P50 to P52 pins also function as on-chip debug pins. The on-chip debug function or port function (including the alternate functions) can be selected by using the level of the DRST pin, as shown in the table below ...
Page 132
... PM52 Control of input/output mode (in port mode) Address: FFFFF44AH PMC52 Specification of operating mode of P52 pin Specification of operating mode of P51 pin Specification of operating mode of P50 pin Address: FFFFF46AH Specification of alternate function of P50 pin User’s Manual U16543EJ4V0UD PM51 PM50 PMC51 PMC50 0 0 PFC50 ...
Page 133
... Do not connect 1 Connect Note An on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode or when the pins function as input pins in the alternate-function mode. An on-chip pull-up resistor cannot be connected when the pins are in output mode. Remark ...
Page 134
... PM5 PM50 TO11 output WR PORT P5 P50 Address RD TIUD11 input Note DRST pin level Note DDI input μ Note PD70F3186 only 132 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P50 Pin Digital noise elimination User’s Manual U16543EJ4V0UD P-ch Note P50/DDI /TIUD11/TO11 ...
Page 135
... Figure 4-23. Block Diagram of P51 and P52 Pins WR PU PU5 PU5n Note DRST pin level WR PMC PMC5 PMC5n WR PM PM5 PM5n WR PORT P5 P5n Address RD TCUD11, TCLR11 input Note DRST pin level Note DCK, DMS input μ Note PD70F3186 only Remark CHAPTER 4 PORT FUNCTIONS ...
Page 136
... Port 7 Port input port with all its pins fixed to the input mode. The number of input port pins differs depending on the product. Commercial Name V850E/IA3 V850E/IA4 Port 7 has an alternate function as the following pins. Table 4-12 Alternate-Function Pins of Port 7 Port Pin No. ...
Page 137
... With the V850E/IA3, be sure to clear these bits to 0. Cautions 1. Do not change to the port mode using A/D converter 2 during A/D conversion. 2. The PMC7 register enables or disables reading of the P7 register. When the PMC7n bit = 1, the input buffer does not turn on even when the P7 register is read. In this case, the read value of the P7n bit is fixed to the low level (V850E/IA3 V850E/IA4 ...
Page 138
... Block diagram Figure 4-24. Block Diagram of P70 to P77 Pins ANI20 to ANI25 input ANI26, ANI27 input WR PMC PMC7 PMC7n RD Note V850E/IA4 only Remark V850E/IA3 V850E/IA4 136 CHAPTER 4 PORT FUNCTIONS P-ch N-ch Note Address User’s Manual U16543EJ4V0UD P70/ANI20 P71/ANI21 P72/ANI22 P73/ANI23 P74/ANI24 ...
Page 139
... PDL15 Notes 1. Software pull-up function 2. This pin is used in the flash programming mode and does not have to be manipulated by a port control register. For details, see CHAPTER 22 FLASH MEMORY. μ 3. PD70F3184 (V850E/IA3), Remark IA3: V850E/IA3 IA4: V850E/IA4 GC (V850E/IA3): 80-pin plastic QFP (14 × 14) GC (V850E/IA4): 100-pin plastic LQFP (fine pitch) (14 × ...
Page 140
... PMDLn 0 1 Note To read/write bits the PMDL register in 8-bit or 1-bit units, specify them as bits the PMDLH register. Remarks 1. The PMDL register can be read or written in 16-bit units. When the higher 8 bits of the PMDL register are used as the PMDLH register, and the lower 8 bits, as the PMDLL register, these registers can be read or written in 8-bit or 1-bit units ...
Page 141
... PUDLn 0 1 Notes 1. To read/write bits the PUDL register in 8-bit or 1-bit units, specify them as bits the PUDLH register on-chip pull-up resistor can be connected only when the pins are in input mode in the port mode. An on-chip pull-up resistor cannot be connected when the pins are in output mode. ...
Page 142
... PMDL PMDLn WR PORT PDL PDLn Address RD Notes 1. This pin is used in the flash programming mode and does not have to be manipulated by a port control register. For details, see CHAPTER 22 FLASH MEMORY. μ 2. PD70F3184 (V850E/IA3), 140 CHAPTER 4 PORT FUNCTIONS Notes 1, 2 FLMD1 input μ ...
Page 143
... Table 4-14 shows the values used to select the alternate function of the respective pins, output data and port read values for each setting. In addition to the settings shown in Table 4-14, the setting of each peripheral function control register is required. CHAPTER 4 PORT FUNCTIONS User’s Manual U16543EJ4V0UD 141 ...
Page 144
... Necessary to specify valid edge Port latch Pin level Port latch Pin level Port latch Pin level Alternate input (timer input) Port latch Pin level Port latch Pin level Port latch Pin level Port latch Pin level Alternate input (timer input) Port latch Pin level ...
Page 145
... Pmn Read Value Remark Port latch Pin level Port latch Pin level Port latch Pin level Alternate input (serial input, timer input) Port latch Pin level Port latch Pin level Port latch Pin level Port latch Pin level Alternate input (serial input) ...
Page 146
... Pin level Port latch Pin level Port latch Pin level Port latch Pin level Output in master mode Port latch Input in slave mode Pin level Port latch Pin level Alternate input (timer input) Port latch Pin level Port latch Pin level Port latch ...
Page 147
... Port 5 Function DRST Pin High-Level Input DRST Pin Low-Level Input DDI Pmn Read Value Remark Port latch Pin level Output in master mode Port latch Input in slave mode Pin level Port latch Pin level Port latch Pin level Alternate input (timer input) ...
Page 148
... The P51 and P52 pins also function as on-chip debug pins ( function) can be selected by using the DRST pin level, as shown in the table below. P51/TCUD11 P52/TCLR11 3. The PDL5 pin is also used in flash programming mode ( manipulated by a port control register. For details, see CHAPTER 22 FLASH MEMORY. Output Data PFCEmn PFCmn PMmn ...
Page 149
... Port Register Settings When Alternate Function Is Used The following shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to the description of each pin. CHAPTER 4 PORT FUNCTIONS User’s Manual U16543EJ4V0UD 147 ...
Page 150
... PM04 = Setting not required PMC04 = 1 PM04 = Setting not required PMC04 = 1 PM05 = Setting not required PMC05 = 1 PM05 = Setting not required PMC05 = 1 PM06 = Setting not required PMC06 = 1 PM07 = Setting not required PMC07 = 1 PM10 = Setting not required PMC10 = 1 PM10 = Setting not required PMC10 = 1 PM10 = Setting not required ...
Page 151
... PM24 = Setting not required PMC24 = 1 PM25 = Setting not required PMC25 = 1 PM26 = Setting not required PMC26 = 1 PM27 = Setting not required PMC27 = 1 PM30 = Setting not required PMC30 = 1 PM31 = Setting not required PMC31 = 1 PM32 = Setting not required PMC32 = 1 PM32 = Setting not required PMC32 = 1 PFCEnx Bit of ...
Page 152
... PM40 = Setting not required PMC40 = 1 PM41 = Setting not required PMC41 = 1 PM42 = Setting not required PMC42 = 1 PM43 = Setting not required PMC43 = 1 PM43 = Setting not required PMC43 = 1 PM44 = Setting not required PMC44 = 1 PM44 = Setting not required PMC44 = 1 PFCEnx Bit of PFCnx Bit of Other Bit ...
Page 153
... Notes 1. V850E/IA4 only μ 2. PD70F3186 (V850E/IA4) only 3. The P50 to P52 pins are also used for on-chip debugging ( function) can be set by setting the DRST pin level. The following shows the setting method. P50/TIUD11/TO11 P51/TCUD11 P52/TCLR11 Table 4-15. Using Port Pin as Alternate-Function Pin (4/5) ...
Page 154
... PDL15 PDL15 = Setting not required PMDL15 = Setting not required Notes 1. V850E/IA4 only 2. The PDL5 pin also functions as a pin to be set in the flash programming mode ( need to be manipulated using the port control register. For details, see CHAPTER 22 FLASH MEMORY. μ μ ...
Page 155
... Noise Eliminator A timing controller used to secure the noise elimination time is provided for the following pins. Input signals that change within the noise elimination time are not internally acknowledged. <R> Unit Reset RESET On-chip debug DRST Mode pin FLMD0 Clock generator (CG) PLLSIN • ...
Page 156
... ENC falling edge detection Caution If there are four or less noise elimination clocks while INTP6 and timer ENC input signals are high level (or low level), the input pulse is eliminated as noise sampled at least five times, the edge is detected as valid input. 154 CHAPTER 4 PORT FUNCTIONS Figure 4-26 ...
Page 157
... External interrupt noise elimination control register (INTPNRC) The INTPNRC register is used to select the sampling clock that is used to eliminate digital noise on the INTP6 pin. If the same level is not detected five times in a row, the signal is eliminated as noise. This register can be read or written in 8-bit or 1-bit units. ...
Page 158
... Noise elimination time select register 1n (NRC1n) (V850E/IA3 V850E/IA4 The NRC1n register is used to select the sampling clock that is used to eliminate digital noise on the TIUD1n, TCUD1n, or TCLR1n pin. If the same level is not detected on these pins five times in a row using the clock selected by the NRC1n register, the signal is eliminated as noise. ...
Page 159
... If the PMCn register is set before setting the PFCn and PFCEn registers, an unexpected peripheral function may be selected while the PFCn and PFCEn registers are being set. (2) An on-chip pull-up resistor can only be connected when the pins are in input mode in the port mode, or when the pins function as input pins in the alternate-function mode. ...
Page 160
... When P20 pin is an output port, P21 to P27 pins are input ports (all pin statuses are high level), and the value of the port latch is 00H, if the output of P20 pin is changed from low level to high level via a bit manipulation instruction, the value of the port latch is FFH. ...
Page 161
... Overview The features of clock generator are as follows. Oscillator • In PLL mode MHz (f X • In clock-through mode MHz (f X Multiply (×8 fixed) function by PLL (Phase Locked Loop) • Clock-through mode/PLL mode selectable Internal system clock generation • 4 steps ( /2, f / Peripheral clock generation ...
Page 162
... Oscillator stop control STOP mode Oscillation stabilization time wait Oscillation stabilization XX Prescaler 1 time wait control (OST) Clock monitor do not go through PLL immediately after reset, and f CLK and f are 1 MHz. CPU CLK Table 5-1. Operation Clock of Each Function Block f (Selected from CPU XX ...
Page 163
... It operates in two modes: clock-through mode in which f control register (PLLCTL), and PLL mode in which a multiplied clock is output. The output frequency of PLL MHz in the PLL mode. When using the frequency in a range MHz ( 6.875 MHz), fix the PLLSIN pin to the low level. When using the frequency in a range of 55 ...
Page 164
... Processor clock control register (PCC) • Power save control register (PSC) • Power save mode register (PSMR) • Oscillation stabilization time select register (OSTS) • Clock monitor mode register (CLM) (1) PLL control register (PLLCTL) The PLLCTL register selects CPU operation clock. ...
Page 165
... Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H. After reset: 03H ...
Page 166
... Power save control register (PSC) The PSC register is a special register. Data can be written to this register only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H ...
Page 167
... Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation in the software standby mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H R/W PSMR 0 0 PSM0 0 IDLE mode ...
Page 168
... STOP mode. Voltage waveform X2 pin 2. The default value of the OSTS register after reset is 04H MHz resonator is used, therefore, the oscillation stabilization time is about 2 ms. Half the oscillation stabilization time is consumed by waiting for the lockup of PLL. Therefore, the actual stabilization time of the resonator is about 1 ms ...
Page 169
... Clock monitor mode register (CLM) The CLM register sets clock monitor operation mode. The CLM register is a special register. It can be written only in a combination of specific sequences (see 3.4.8 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. ...
Page 170
... Fix the input level of the PLLSIN pin to the high or low level according to the value the PLL mode, the clock is input from the oscillator to the PLL. A clock at a stable frequency must be supplied to the internal circuit after the lapse of the lockup time (frequency stabilization time) during which the phase is locked at a specific frequency and oscillation is stabilized ...
Page 171
... During RESET pin input and subsequent oscillation stabilization time count Notes 1. The peripheral clock (f 2. Operation continues during on-chip debugging. 3. The watchdog timer clock is not output from the prescaler (PRS). Remark √: Operating ×: Stopped CHAPTER 5 CLOCK GENERATOR Table 5-3. Operation Status of Each Clock ...
Page 172
... When the fixed oscillation stabilization time that elapses after the RESET signal is released expires, PLL stop is released, and counting the lockup time starts. <3> PLL is locked when counting of the lockup time is over. The OST counter is initialized to 00H. <4> When the lockup time expires, the CPU releases the reset signal and operates in the clock-through mode (f ) ...
Page 173
... When the fixed oscillation stabilization time that elapses after the reset signal is released expires, PLL stop is released, and counting the lockup time starts. <3> PLL is locked when counting of the lockup time is over. The OST counter is initialized to 00H. <4> When the lockup time expires, the CPU releases the reset signal and operates in the clock-through mode (f ) ...
Page 174
... After half the oscillation stabilization time has elapsed, the lockup wait time starts. The remaining count time of the OST counter is the lockup wait time. <5> When the lockup time of PLL is over, clock supply to the internal circuitry is started. At this time, the status before the STOP mode was set is recovered. ...
Page 175
... Clock monitor function The clock monitor samples the clock generated by the oscillator, by using the internal oscillation clock. When it detects stop of oscillation, output of the timer for motor control goes into a high-impedance state (for details, see CHAPTER 10 MOTOR CONTROL FUNCTION). CHAPTER 5 CLOCK GENERATOR User’ ...
Page 176
... Overflow interrupt request signal Timer output pin Notes 1. Compare function only 2. V850E/IA3: None V850E/IA4: 1 6.2 Functions The functions of TMPn that can be realized differ from one channel to another, as shown in the table below ( 3). Function Interval timer External event counter External trigger pulse output One-shot pulse output ...
Page 177
... Notes 1. The TIP00 and TIP20 pins function alternately as a capture input signal, external event count input signal, and external trigger input signal. 2. Not provided for TMP1 and TMP3 3. V850E/IA4 only 4. Not provided for TMP1 Remark V850E/IA3 V850E/IA4 Table 6-3. Configuration of TMPn Configuration Note1 Note 1 Note 2 , TIP01, TIP20 ...
Page 178
... CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP / / / /128 XX f /256 XX TIP00 TIP01 Remark f : Peripheral clock / / / /128 XX f /256 XX Remark f : Peripheral clock XX 176 Figure 6-1. TMP0 Block Diagram Internal bus TP0CNT 16-bit counter CCR0 buffer CCR1 register buffer register TP0CCR0 TP0CCR1 Internal bus Figure 6-2. TMP1 Block Diagram ...
Page 179
... XX f /256 XX TIP20 TIP21 TOP2OFF Remarks Peripheral clock XX 2. For the TOP2OFF pin, see 10.3 (6) High-impedance output control registers 00, 01, 10, 11, 20, 21 (HZAmCTL0, HZAmCTL1). Figure 6-3. TMP2 Block Diagram Internal bus TP2CNT 16-bit counter CCR0 buffer CCR1 register buffer register ...
Page 180
... This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR0 register is used as a compare register, the value written to the TPnCCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. ...
Page 181
... This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. ...
Page 182
... TOP01, TOP21, and TOP31 (V850E/IA4 only) pins) as the 16-bit counter are reset to the TPmIOC0 register set status at the same time. Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0. When the value of the TPnCE bit is changed from the TPnCKS2 to TPnCKS0 bits can be set simultaneously sure to clear bits “0”. ...
Page 183
... The TPkEEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. Notes 1. This bit can only be set in TMP0 and TMP1. Be sure to clear bit 7 of TMP2 and TMP3 to 0. For details of tuning operation mode, see CHAPTER 10 MOTOR CONTROL FUNCTION. ...
Page 184
... Note The settings that can be realized differ from one channel to another. For details, see Tables 6-8 to 6-11. Cautions 1. The TPmEST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. ...
Page 185
... V850E/IA4 Notes 1. V850E/IA4 only 2. Valid only for TMP0. Be sure to clear bits 1 and 0 of TMP2 and TMP3 The output level of the timer output pins (TOP00 and TOPm1) specified by the TPmOLa ( bit is shown below ( 1). <R> TOP00, TOPm1 <R> Caution 1. If the setting of the TPmIOC0 register is changed when TOP00 and TOPm1 are set in the output mode, the output of the pins change ...
Page 186
... CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions 2. Rewrite the TPmOL1, TPmOE1, TP0OL0, and TP0OE0 bits when the TPmCTL0.TPnCE bit = 0. (The same value can be written when the TPmCE bit = 1.) If rewriting was mistakenly performed, clear the TPmCE bit to 0 and then set the bits again. ...
Page 187
... TPkCE bit = 1.) If rewriting was mistakenly performed, clear the TPkCE bit to 0 and then set the bits again. 2. The TPkIS3 to TPkIS0 bits are valid only in the free-running timer mode (only when the TPnOPT0.TPkCCS1, TPkCCS0 bits = 11) and the pulse width measurement mode. In all other modes, a capture operation is not possible (TMP0, TMP2 only) ...
Page 188
... Cautions 1. Rewrite the TPkEES1, TPkEES0, TPkETS1, and TPkETS0 bits when the TPkCTL0.TPkCE bit = 0. (The same value can be written when the TPkCE bit = 1.) If rewriting was mistakenly performed, clear the TPkCE bit to 0 and then set the bits again. 2. The TPkEES1 and TPkEES0 bits are valid only when the TPkCTL1.TPkEEE bit = 1 or when the external event count mode (TPkCTL1 ...
Page 189
... The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set software. Writing 1 has no effect on the operation of TMPn. Note Valid only for TMP0 and TMP2. Be sure to clear bits 5 and 4 of TMP1 and TMP3 to 0. Cautions 1. Rewrite the TPkCCS1 and TPkCCS0 bits when the TPkCE bit = 0. (The same value can be written when the TPkCE bit = 1 ...
Page 190
... The TP1CCR0 and TP3CCR0 registers are 16-bit registers that can only be used as compare registers. The TP0CCR0 and TP2CCR0 registers can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS0 or TP2OPT0.TP2CCS0 bit. In the pulse width measurement mode, the TPnCCR0 register can be used only as a capture register ...
Page 191
... The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated. If TOP00 pin output is enabled at this time, the output of the TOP00 pin is inverted (TOP10, TOP20, and TOP30 pins are not provided). ...
Page 192
... The TP1CCR1 and TP3CCR1 registers are 16-bit registers that can only be used as compare registers. The TP0CCR1 and TP2CCR1 registers can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS1 or TP2OPT0.TP2CCS1 bit. In the pulse width measurement mode, the TPnCCR1 register can be used only as a capture register ...
Page 193
... The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated. If TOPm1 pin output is enabled at this time, the output of the TOPm1 pin is inverted (the TOP11 pin is not provided). ...
Page 194
... The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0. If the TPnCNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TPnCE bit is cleared to 0 after reset, and the TPnCNT register is cleared to 0000H. ...
Page 195
... External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Remark V850E/IA3 V850E/IA4 Table 6-7. Truth Table of TOP00 and TOPm1 Pins Under Control of Timer Output Control Bits TPmIOC0.TPmOLa Bit TPmIOC0.TPmOEa Bit ...
Page 196
... CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP) 6.6 Operation The functions of TMPn that can be realized differ from one channel to another. The functions of each channel are shown below. Table 6-8. TMP0 Specifications in Each Mode Operation TP0CTL1.TP0EST Bit (Software Trigger Bit) Interval timer mode Invalid ...
Page 197
... Pulse width measurement mode Invalid Notes 1. When using the external event count mode, set the TIP20 pin capture trigger input valid edge selection to “No edge detection”. (Clear the TP2IOC1.TP2IS1 and TO2IOC1.TP2IS0 bits to 00.) 2. When using the external trigger pulse output mode and one-shot pulse output mode, select the internal clock as the count clock (by clearing the TP2CTL1 ...
Page 198
... In external event count mode When the TPkCTL0.TPkCE bit is set from the 16-bit counter is set to 0000H. After that, it counts up from 0001H to 0002H, 0003H, and so on, each time the valid edge of an external event count input (TIPk0) is detected. • In modes other than the above The 16-bit counter of TMPn starts counting from the default value FFFFH ...
Page 199
... Note The 16-bit counter is not cleared upon a match between the value of the16-bit counter and the value of the CCR1 buffer register cleared upon a match between the value of the 16-bit counter and the value of the CCR0 buffer register. ...
Page 200
... CCR0 buffer register and the value of the 16-bit counter. Transfer is enabled by writing to the TPmCCR1 register. Whether to enable or disable the next transfer timing is controlled by writing or not writing to the TPmCCR1 register. In order for the setting value when the TPmCCR0 and TPmCCR1 registers are rewritten to become the 16- ...