M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 198

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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196
(1) Counter basic operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the
operation in each mode.
Remark
(a) Counter start operation
(b) Clear operation
(c) Overflow operation
(d) Counter read operation during counting operation
(e) Interrupt operation
• In external event count mode
• In modes other than the above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and is
cleared, and when its value is captured and cleared. The counting operation from FFFFH to 0000H that
takes place immediately after the counter has started counting or when the counter overflows is not a
clearing operation. Therefore, the INTTPnCC0 and INTTPnCC1 interrupt signals are not generated.
The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running timer
mode or pulse width measurement mode. If the counter overflows, the TPnOPT0.TPnOVF bit is set to 1
and an interrupt request signal (INTTPnOV) is generated. Note that the INTTPnOV signal is not generated
under the following conditions.
• Immediately after a counting operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared in the pulse width measurement mode and the counter counts up
Caution After the overflow interrupt request signal (INTTPnOV) has been generated, be sure to
The value of the 16-bit counter of TMPn can be read by using the TPnCNT register during the count
operation. When the TPnCTL0.TPnCE bit = 1, the value of the 16-bit counter can be read by reading the
TPnCNT register. However, when the TPnCTL0.TPnCE bit = 0, the 16-bit counter is FFFFH and the
TPnCNT register is 0000H.
TMPn generates the following three types of interrupt request signals.
• INTTPnCC0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer
• INTTPnCC1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer
• INTTPnOV interrupt:
from FFFFH to 0000H
When the TPkCTL0.TPkCE bit is set from 0 to 1, the 16-bit counter is set to 0000H.
After that, it counts up from 0001H to 0002H, 0003H, and so on, each time the valid edge of an external
event count input (TIPk0) is detected.
The 16-bit counter of TMPn starts counting from the default value FFFFH.
It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on.
n = 0 to 3, k = 0, 2
check that the overflow flag (TPnOVF bit) is set to 1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
register and as a capture interrupt request signal to the TPnCCR0 register.
register and as a capture interrupt request signal to the TPnCCR1 register.
This signal functions as an overflow interrupt request signal.
User’s Manual U16543EJ4V0UD