M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 411

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
(3) Operation in UDC mode A
(a) Interval operation
(b) Transfer operation
(c) Compare function
(d) Capture function
The operations at the count clock following a match of the TMENC1n count value and the CM1n0 register
set value are as follows.
• In case of count up operation:
• In case of count down operation: The TMENC1n count value is decremented (−1) and the INTCMn0
If TMENC1n = 0000H during counting down when the TMC1n.RLENn bit = 1, the set value of the CM1n0
register is transferred to TMENC1n at the next count clock.
TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TMENC1n count value and the set value of one of the compare registers match, a match
interrupt request signal (INTCMn0, INTCMn1, INTCCn0
Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to
TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels.
When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is
captured in synchronization with the corresponding capture trigger signal.
request signal (INTCCn0, INTCCn1) is generated upon detection of the valid edge.
Remark
Remarks 1. Transfer enable/disable can be set using the TMC1n.RLENn bit.
the compare register mode.
Figure 8-10. Example of TMENC1n Operation When Interval Operation and
2. The transfer operation can be combined with an interval operation.
The interval operation can be combined with a transfer operation.
CM1n0 register set value
TMENC1n count value
Transfer Operation Are Combined
0000H
User’s Manual U16543EJ4V0UD
TMENC1n is cleared (0000H) and the INTCMn0 interrupt request
signal is generated.
interrupt request signal is generated.
TMENC1n and CM1n0
match & timer clear
Count up
Note
, INTCCn1
& CM1n0 data transfer
TMENC1n underflow
Count down
Note
) is output.
Also, a capture interrupt
409