M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 14

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 571
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB)............................................................... 598
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) ................................................................. 643
12
14.1 Mode Switching Between UARTA1 and CSIB1 ................................................................... 571
14.2 Features .................................................................................................................................. 572
14.3 Configuration.......................................................................................................................... 573
14.4 Control Registers ................................................................................................................... 575
14.5 Interrupt Request Signals ..................................................................................................... 580
14.6 Operation ................................................................................................................................ 581
14.7 Dedicated Baud Rate Generator........................................................................................... 590
14.8 Cautions .................................................................................................................................. 597
15.1 Mode Switching Between UARTA1 and CSIB1 ................................................................... 598
15.2 Features .................................................................................................................................. 599
15.3 Configuration.......................................................................................................................... 600
15.4 Control Registers ................................................................................................................... 602
15.5 Operation ................................................................................................................................ 609
15.6 Output Pins ............................................................................................................................. 642
16.1 Features .................................................................................................................................. 643
16.2 Configuration.......................................................................................................................... 644
16.3 Control Registers ................................................................................................................... 645
13.7.1 Writing to the ADA2CTL1 and ADA2CTL3 registers during conversion......................................569
13.7.2 Conflict with timing of storing data in the conversion result register............................................569
14.6.1 Data format .................................................................................................................................581
14.6.2 UART transmission .....................................................................................................................583
14.6.3 Continuous transmission procedure............................................................................................584
14.6.4 UART reception ..........................................................................................................................586
14.6.5 Reception errors .........................................................................................................................587
14.6.6 Parity types and operations ........................................................................................................588
14.6.7 Receive data noise filter..............................................................................................................589
15.5.1 Single transfer mode (master mode, transmission mode)...........................................................609
15.5.2 Single transfer mode (master mode, reception mode) ................................................................611
15.5.3 Single transfer mode (master mode, transmission/reception mode) ...........................................613
15.5.4 Single transfer mode (slave mode, transmission mode) .............................................................615
15.5.5 Single transfer mode (slave mode, reception mode)...................................................................617
15.5.6 Single transfer mode (slave mode, transmission/reception mode)..............................................619
15.5.7 Continuous transfer mode (master mode, transmission mode)...................................................621
15.5.8 Continuous transfer mode (master mode, reception mode) ........................................................623
15.5.9 Continuous transfer mode (master mode, transmission/reception mode) ...................................626
15.5.10 Continuous transfer mode (slave mode, transmission mode) .....................................................630
15.5.11 Continuous transfer mode (slave mode, reception mode) ..........................................................632
15.5.12 Continuous transfer mode (slave mode, transmission/reception mode) .....................................635
15.5.13 Reception error ...........................................................................................................................639
15.5.14 Clock timing ................................................................................................................................640
16.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)...............................................................645
16.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)........................................................647
User’s Manual U16543EJ4V0UD