M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 400

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

398
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
(7) CC1n1 capture input select register (CSL1n)
(8) Noise elimination time select register 1n (NRC1n)
Note V850E/IA4 only
Note V850E/IA4 only
The CSL1n register is used to select the TCLR1n or TCUD1n pin to input a capture signal when the CC1n1
register is used as a capture register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The NRC1n register selects the sampling clock that is used to eliminate digital noise on the TIUD1n, TCUD1n,
or TCLR1n pin. If a level is not detected on these pins five times in a row at the clock selected by the NRC1n
register, the signal is eliminated as noise.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Cautions 1. If the input pulse is 4- to 5-clock width, it is undefined whether the pulse is detected as a
V850E/IA3
V850E/IA4
V850E/IA3
V850E/IA4
n = 0, 1
2. If noise is generated in synchronization with the sampling clock, eliminate the noise by
3. Noise is not eliminated if the pin is used as a normal input port pin.
4. The noise elimination function starts operating when the TMC1n.TM1CEn bit is set to 1
n = 0, 1
After reset: 00H
NRC1n
After reset: 00H
CSL1n
n = 0
n = 0
valid edge or eliminated as noise. So that the pulse is actually detected as a valid edge, a
pulse level must be input for the duration of 5 clocks or more.
attaching a filter to the input pin.
(enabling count operations).
NRC1n1
CSL1n0
0
0
1
1
0
1
7
0
7
0
TCLR1n
TCUD1n
NRC1n0
R/W
R/W
6
0
0
1
0
1
6
0
input
User’s Manual U16543EJ4V0UD
input
Address: NRC10 FFFFF598H, NRC11 FFFFF5B8H
Address: CSL10 FFFFF596H, CSL11 FFFFF5B6H
f
f
f
f
Selection of capture input signal of CC1n1 register
XX
XX
XX
XX
/32
/16
/8
/4
5
0
5
0
4
0
4
0
Sampling clock selection
3
0
3
0
0
0
2
2
NRC1n1 NRC1n0
1
1
0
Note
Note
CSL1n0
0
0