M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 472

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

470
(3) Intermittent batch rewriting mode (transfer culling mode)
This mode is set when the TQnOPT0.TQnCMS bit is 0 and the TQnOPT2.TQnRDE bit is 1.
In this mode, the values written to each compare register are transferred to the internal buffer register all at
once at the culled transfer timing and compared with the counter value.
The transfer timing is the timing at which an interrupt is generated (INTTQnCC0, INTTQnOV) by interrupt
culling.
For details of the interrupt culling function, see 10.4.3 Interrupt culling function.
(a) Rewriting procedure
If data is written to the TQnCCR1 register, the TQnCCR0 to TQnCCR3, TQnOPT1, TPnCCR0, and
TPnCCR1 registers are transferred all at once to the internal buffer register at the next transfer timing.
Therefore, write to the TQnCCR1 register last. Writing to the register is prohibited after the TQ0CCR1
register has been written until the transfer timing is generated (until the INTTQnOV or INTTQnCC0
interrupt occurs). The operation procedure is as follows.
<1> Rewrite the TQnCCR0, TQnCCR2, TQnCCR3, TQnOPT1, TPnCCR0, and TPnCCR1 registers.
<2> Rewrite the TQnCCR1 register.
<3> Hold the next rewriting pending until the transfer timing is generated.
<4> Return to <1>.
Do not rewrite registers that do not have to be rewritten.
Rewrite the same value to the register even when it is not necessary to rewrite the TQnCCR1
register.
Perform the next rewrite after the INTTQnOV or INTTQnCC0 interrupt has occurred.
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U16543EJ4V0UD