M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 240

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
<R>
<R>
238
TPkIOC2
(d) TMPk I/O control register 2 (TPkIOC2)
(e) TMPm counter read buffer register (TPmCNT)
(f) TMPm capture/compare registers 0 and 1 (TPmCCR0 and TPmCCR1)
The value of the 16-bit counter can be read by reading the TPmCNT register.
If D
delay period of the one-shot pulse are as follows.
Active level width = (D
Output delay period = D
Caution One-shot pulses are not output even in the one-shot pulse output mode, if the value
Remarks 1. TMPk I/O control register 1 (TPkIOC1) and TMPm option register 0 (TPmOPT0) are not
0
0
is set to the TPmCCR0 register and D
Figure 6-29. Setting of Registers in One-Shot Pulse Output Mode (2/2)
set in the TPmCCR1 register is greater than that set in the TPmCCR0 register.
2. V850E/IA3: m = 0, 2, k = 0, 2
used in the one-shot pulse output mode.
V850E/IA4: m = 0, 2, 3, k = 0, 2
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0
− D
1
0
× Count clock cycle
1
+ 1) × Count clock cycle
0
User’s Manual U16543EJ4V0UD
TPkEES1
0
1
to the TPmCCR1 register, the active level width and output
TPkEES0 TPkETS1 TPkETS0
0
0/1
0/1
Select valid edge of
external trigger input (TIPk0 pin)

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