M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 163

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
(1) Oscillator
(2) IDLE control
(3) HALT control
(4) PLL
(5) Prescaler 1
(6) Prescaler 2
(7) Oscillation stabilization time wait control (OST)
(8) Clock monitor
The main resonator oscillates the following frequencies (f
• In PLL mode (×8 fixed): f
• In clock-through mode: f
All functions other than the oscillator, PLL, clock monitor operation, and CSIB in slave mode are stopped.
Only the CPU clock (f
This circuit multiplies the clock generated by the oscillator (f
It operates in two modes: clock-through mode in which f
control register (PLLCTL), and PLL mode in which a multiplied clock is output.
The output frequency of PLL is 32 to 64 MHz in the PLL mode. When using the frequency in a range of 32 to
55 MHz (f
to 64 MHz (f
This prescaler generates the clock (f
This circuit divides the system clock (f
The clock (f
This unit measures the time from when the clock generated by the oscillator was input until oscillation is
stabilized. It also counts the PLL lockup time.
The count clock can be selected from 2
The clock monitor samples the clock generated by the oscillator (f
When it detects stop of oscillation, output of the timer for motor control goes into a high-impedance state (for
details, see CHAPTER 10 MOTOR CONTROL FUNCTION).
X
= 4 to 6.875 MHz), fix the PLLSIN pin to the low level. When using the frequency in a range of 55
XX
X
= 6.876 to 8 MHz), fix the PLLSIN pin to the high level.
to f
XX
/8) to be supplied to the CPU clock (f
CPU
) is stopped.
X
X
= 4 to 8 MHz (f
= 4 to 8 MHz (f
CHAPTER 5 CLOCK GENERATOR
XX
XX
User’s Manual U16543EJ4V0UD
to f
14
).
/f
X
XX
XX
to 2
XX
/4,096) to be supplied to on-chip peripheral functions.
= 4 to 8 MHz)
= 32 to 64 MHz)
18
/f
X
.
CPU
X
X
):
is output as is by setting the SELPLL bit of the PLL
) and internal system clock (f
X
) by 8.
X
), by using the internal oscillation clock.
CLK
) is generated.
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