M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 57

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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(6) Exception/debug trap status saving registers (DBPC, DBPSW)
(7) CALLT base pointer (CTBP)
DBPSW
CTBP
DBPC
There are two exception/debug trap status saving registers, DBPC and DBPSW.
Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to
DBPC, and the program status word (PSW) contents are saved to DBPSW.
The contents saved to DBPC consist of the address of the next instruction after the instruction executed when
an exception trap or debug trap occurs.
The current PSW contents are saved to DBPSW.
These registers can be read or written only in the period between DBTRAP instruction or illegal opcode
execution and DBRET instruction execution.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.
When the DBRET instruction has been executed, the values of DBPC and DBPSW are restored to the PC and
PSW, respectively.
The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is
fixed to 0).
Bits 31 to 26 are reserved (fixed to 0) for future function expansion.
31
0
31
31
0
0
0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
26 25
26 25
0
0
0 0 0 0
CHAPTER 3 CPU FUNCTION
User’s Manual U16543EJ4V0UD
0
0
0 0 0 0
(PC contents saved)
(Base address)
0
0
0 0 0 0
8
(PSW contents saved)
7
0
0
0
0
(x: Undefined)
(x: Undefined)
(x: Undefined)
0xxxxxxxH
After reset
000000xxH
0xxxxxxxH
After reset
After reset
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