M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 568

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

566
A/D2 conversion
result register n
(3) 4-buffer serial mode
Figure 13-6. Example of Operation Timing in 4-Buffer Serial Mode (with 8-Bit Resolution, f
Remarks 1. Data:
Notes 1. The ANI26 and ANI27 pins are only available in the V850E/IA4.
A/D conversion of the analog input pin (ANI2n)
times, and the four conversion results are stored in four A/D2 conversion result registers n (ADA2CRn) (n = 0
to 7).
The conversion results of one of the ANI20 to ANI23 pins are stored in the ADA2CR0 to ADA2CR3 registers,
and those of one of the ANI24 to ANI27 pins
Figure 13-2).
The A/D2 conversion end interrupt request signal (INTAD2) is generated when the A/D conversion has been
ended four times. After end of the A/D conversion, it is repeated again with the same ANI2n pin
ADA2CTL0.ADA2CE bit is cleared to 0 (conversion stopped).
It is not required to set (1) the ADA2CTL0.ADA2CE bit to restart A/D conversion
A/D conversion can be stopped by clearing the ADA2CE bit to 0.
INTAD2 interrupt
2. In 4-buffer serial mode, unless the ADA2CTL0.ADA2CE bit is cleared to 0, A/D conversion is not
2. n = 0 to 7
3. f
ADA2CE bit
DF counter
ADA2CR0
ADA2CR1
ADA2CR2
ADA2CR3
stopped. Therefore, the contents of the ADA2CRn register must be read before A/D conversion
ends, or the register is overwritten (n = 0 to 7).
DF counter: Digital filter
The A/D conversion results of one of the ANI20 to ANI23 pins are stored in the ADA2CR0 to
ADA2CR3 registers.
The A/D conversion results of one of the ANI24 to ANI27 pins are stored in the ADA2CR4 to
ADA2CR7 registers.
The above chart shows an example of the operation timing when one of the ANI20 to ANI23
pins is selected.
XX
: Peripheral clock
Conversion data
Data 0
CHAPTER 13 A/D CONVERTER 2
User’s Manual U16543EJ4V0UD
Data 1
Data 0
512 s + 6 clocks
μ
Note 1
Note 1
are stored in the ADA2CR4 to ADA2CR7 registers (see
specified by the ADA2CTL2 register is performed four
Data 2
Data 1
Data 3
Data 2
Note 2
.
Data 4
Data 3
512 s
XX
μ
Note 1
= 64 MHz)
Data 5
, unless the
Data 4