M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 564

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13.4.2 Buffer mode and operation mode
pin (ANI2n)
562
1-buffer
4-buffer
Buffer Mode
With A/D converter 2, continuous conversion and time difference conversion can be specified for one analog input
The buffer mode and operation mode are specified by the ADA2CTL3 register.
Note The ANI26 and ANI27 pins are only available in the V850E/IA4.
Notes 1. With 8-bit resolution, f
(1) Buffer mode
The result of A/D conversion of one analog input pin (ANI2n)
mode and 4-buffer mode (n = 0 to 7).
These buffer modes are selected by the ADA2CTL3.ADA2BS bit.
Note The ANI26 and ANI27 pins are only available in the V850E/IA4.
(a) 1-buffer mode
(b) In 4-buffer mode
2. The ANI26 and ANI27 pins are only available in to the V850E/IA4.
3. Time until the ADA2CR0 or ADA2CR4 register is updated as a result of the first A/D conversion after
Note
In this mode, the analog input pin (ANI2n)
result register n (ADA2CRn) correspond one to one (see Table 13-2) (n = 0 to 7).
Note The ANI26 and ANI27 pins are only available in the V850E/IA4.
The voltage of the analog input pin (ANI2n)
times, and the results are stored in four A/D2 conversion result registers (ADA2CRn) (n = 0 to 7).
The conversion result of one of the ANI20 to ANI23 pins is stored in the ADA2CR0 to ADA2CR3 registers,
and the result of one of the ANI24 to ANI27 pins
Figure 13-2).
Note The ANI26 and ANI27 pins are only available in the V850E/IA4.
Serial mode
Parallel mode
Serial mode
Parallel mode
generation of the A/D2 conversion end interrupt request signal (INTAD2)
specified by the ADA2CTL2 register (n = 0 to 7).
Operation
Mode
ANI2n
ANI2n
One of ANI20 to ANI23
One of ANI24 to ANI27
One of ANI20 to ANI23
One of ANI24 to ANI27
Analog Input Pin
Note 2
Note 2
XX
= 64 MHz
CHAPTER 13 A/D CONVERTER 2
User’s Manual U16543EJ4V0UD
Note 2
Note 2
ADA2CRn
ADA2CRn
ADA2CR0 to ADA2CR3
ADA2CR4 to ADA2CR7
ADA2CR0 to ADA2CR3
ADA2CR4 to ADA2CR7
A/D Conversion Result
Note
Note
specified by the ADA2CTL2 register and A/D2 conversion
specified by the ADA2CTL2 register is A/D converted four
Note
Register
is stored in the ADA2CR4 to ADA2CR7 registers (see
Note
can be stored in two buffer modes: 1-buffer
128
32
512
128
Interrupt Occurrence
μ
μ
μ
μ
s
Interval
s
s
s
Note 1
128
32
128
32
Conversion Result
μ
μ
Read Pending
μ
s
μ
s
Note 3
s
s
Period
Note 3
Note 1

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