M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 579

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(4) UARTAn option control register 0 (UAnOPT0)
(5) UARTAn status register (UAnSTR)
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the
UAnPE, UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by
writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained).
The initialization conditions are shown below.
Caution Be sure to read and check the error flags of the UAnPE, UAnFE, and UAnOVE bits, and clear
UAnOPT0
UAnSTR register
UAnTSF bit
UAnPE, UAnFE, UAnOVE bits
(n = 0, 1)
the flags by writing “0” to them.
After reset: 14H
Caution Be sure to clear bits 3 and 5 to 7 to “0”, and set bits 2 and 4 to
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnTDL
• The output level of the TXDAn pin can be inverted using the UAnTDL bit.
• This register can be set when the UAnCTL0.UAnPWR bit = 0 or when the
UAnRDL
• The input level of the RXDAn pin can be inverted using the UAnRDL bit.
• This register can be set when the UAnPWR bit = 0 or the UAnCTL0.UAnRXE bit = 0.
• When the UAnRDL bit is set to 1 (inverted input of receive data), reception must be
enabled (UAnCTL0.UAnRXE bit = 1) after setting the data reception pin to the
UART reception pin (RXDAn) when reception is started. When the pin mode is
changed after reception is enabled, the start bit will be mistakenly detected if the
pin level is high.
UAnCTL0.UAnTXE bit = 0.
0
1
0
1
0
7
Register/Bit
Normal output of transfer data
Inverted output of transfer data
Normal input of transfer data
Inverted input of transfer data
“1”. Operation with other settings is not guaranteed.
R/W
6
0
Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H
User’s Manual U16543EJ4V0UD
5
0
4
1
Transmit data level bit
Receive data level bit
• After reset
• UAnCTL0.UAnPWR bit = 0
• UAnCTL0.UAnTXE bit = 0
• 0 write
• UAnCTL0.UAnRXE bit = 0
3
0
Initialization Conditions
2
1
UAnTDL UAnRDL
1
0
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