M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 493

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
12.2 Configuration
The block diagram is shown below.
Note In the V850E/IA3, only ANI12 and ANI13 are valid.
Remark
Cautions 1. If there is noise at the analog input pins (ANIn0 to ANIn3 (only ANI00 and ANI01 for A/D
ADAnM2
n = 0, 1
m = 0 to 3 (when using the operational amplifier for input level amplification: m = 4 to 7)
ANIn2
ANIn3
CMPREF
ADTRGn
TTRGn0
TTRGn1
Trigger source selector in timer trigger
ADAnBS
2. Do not apply a voltage outside the AV
ANIn0
ANIn1
Note
Note
modes 0, 1 (see FIgure 12-3)
converter 0 of the V850E/IA3)) or at the A/D converter power supply voltage pin (AV
that noise may generate an illegal conversion result (n = 0, 1).
Software processing will be needed to avoid a negative effect on the system from this
illegal conversion result.
An example of this software processing is shown below.
• Take the average result of a number of A/D conversions and use that as the A/D
• Execute a number of A/D conversions consecutively and use those results, omitting
• If an A/D conversion result that is judged to have generated a system malfunction is
pins of A/D converters 0 and 1.
ADAnTMD1ADAnTMD0
Input circuit (see Figure 12-2)
conversion result.
any exceptional results that may have been obtained.
obtained, be sure to recheck the system malfunction before performing malfunction
processing.
ADAnS
ADAnM0
CMP
CMP
CMP
Figure 12-1. Block Diagram of A/D Converters 0 and 1
AMP
AMP
AMP
ADAnS2 ADAnS1 ADAnS0
Edge detection/
noise eliminator
ADAnCE ADAnMD1ADAnMD0
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD
INTCMPn
To high-impedance controller
of timer output for motor
control
ADAnETS1 ADAnETS0 ADAnTMD ADAnEF
Sample & hold circuit
Internal bus
SS
ADAnM1
to AV
Controller
ADAnFR1 ADAnFR0
A/Dn conversion result register m
Counter
DD
approximation
register (SAR)
Successive
(ADAnCRm/ADAnCRmH)
range to the pins that are used as input
comparator
Voltage
Array
AV
DD
INTADn
AV
SS
491
DD
),

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