M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 220

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
218
(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, the TPkCCR0 and TPkCCR1 registers must not be
(a) Operation if TPkCCR0 register is set to FFFFH
If the TPkCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of
the external event count signal has been detected.
synchronization with the next count-up timing, and the INTTPkCC0 signal is generated. At this time, the
TPkOPT0.TPkOVF bit is not set.
Remark
2. In the external event count mode, use of the timer output (TOP00, TOPk1) is disabled. If
INTTPkCC0 signal
TPkCCR0 register
cleared to 0000H.
performing timer output (TOPk1) using external event count input (TIPk0), set the interval
timer mode, and enable the count clock operation with the external event count input
(TPkCTL1.TPkEEE bit = 1) (see 6.6.1 (3) Operation by external event count input (TIPk0)).
k = 0, 2
16-bit counter
TPkCE bit
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
External event
count: FFFFH
User’s Manual U16543EJ4V0UD
External event
count: 10000H
FFFFH
The 16-bit counter is cleared to 0000H in
External event
count: 10000H

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