M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 169

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(6) Clock monitor mode register (CLM)
Cautions 1. The CLME bit is cleared to 0 only after reset.
The CLM register sets clock monitor operation mode. The CLM register is a special register. It can be written
only in a combination of specific sequences (see 3.4.8 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. When the CLME bit = 1, the clock monitor function is forcibly stopped if the following
3. When the CLME bit = 1, output of the timer for motor control goes into a high-impedance
After reset: 00H
CLM
conditions are satisfied.
• During oscillation stabilization time count after release of STOP mode
• During break (on-chip debug emulator)
state if oscillation (f
CLME
0
1
0
Clock monitor operation disabled
Clock monitor operation enabled
R/W
0
X
) stop is detected. See Figure 10-4 for the target timer output.
CHAPTER 5 CLOCK GENERATOR
Address: FFFFF870H
User’s Manual U16543EJ4V0UD
0
Clock monitor operation control
0
0
0
0
CLME
167

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