M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 430

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
<R>
<R>
<R>
428
(2) TMQn option register 1 (TQnOPT1)
Notes 1. V850E/IA4 only
The TQnOPT1 register is an 8-bit register that controls the interrupt request signal generated by the timer Qn
option function.
The TQnOPT1 register generates the signals output to the interrupt culling circuit, A/D trigger generator 1, and
A/D trigger generator 2 shown in Figure 10-2.
This register can be rewritten when the TQnCTL0.TQnCE bit is 1.
Two rewriting modes (batch write mode and anytime write mode) can be selected, depending on the setting of
the TQnOPT0.TQnCMS bit.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. When using the crest interrupt (INTTQnCC0 signal) and the valley interrupt (INTTQnOV signal) as
V850E/IA3
V850E/IA4
the count signal for interrupt culling or as the A/D trigger signal, set the signal to be used to 1.
A/D trigger is generated at the culled interrupt timing.
TQnOPT1
n = 0, 1
n = 0
After reset: 00H
TQnID4
TQnICE
TQnIOE
TQnICE
0
0
0
0
1
1
1
1
<7>
:
0
1
0
1
TQnID3
CHAPTER 10 MOTOR CONTROL FUNCTION
TQnIOE
Do not use INTTQnCC0 signal (do not use it as count signal for interrupt
culling).
Use INTTQnCC0 signal (use it as count signal for interrupt culling).
Do not use INTTQnOV signal (do not use it as count signal for interrupt
culling).
Use INTTQnOV signal (use it as count signal for interrupt culling).
0
0
0
0
1
1
1
1
:
R/W
<6>
TQnID2
User’s Manual U16543EJ4V0UD
0
0
0
0
1
1
1
1
:
Address: TQ0OPT1 FFFFF5E0H, TQ1OPT1 FFFFF620H
Crest interrupt (INTTQnCC0 signal) enable
Valley interrupt (INTTQnOV signal) enable
5
0
TQnID1
0
0
1
1
0
0
1
1
:
TQnID4
4
TQnID0
0
1
0
1
0
1
0
1
:
TQnID3
Not culled (all interrupts are output)
1 masked (one of two interrupts is output)
2 masked (one of three interrupts is output)
3 masked (one of four interrupts is output)
28 masked (one of 29 interrupts is output)
29 masked (one of 30 interrupts is output)
30 masked (one of 31 interrupts is output)
31 masked (one of 32 interrupts is output)
3
Number of times of interrupt
TQnID2
2
:
TQnID1
Note 2
Note 2
1
TQnID0
0
Note 1