M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 511

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
12.4 Operation
12.4.1 Basic operation
Cautions 1. A/D converters 0 and 1 are capable of simultaneous sampling of two circuits.
A/D conversion is executed by the following procedure.
(1) Select an analog input pin, operation mode, and trigger mode, by using the ADAnM0, ADAnM1, ADAnM2, and
Note If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, or if a valid trigger is
(2) In the software trigger mode, setting the ADAnM0.ADAnCE bit to 1 starts A/D conversion after the lapse of the
(3) When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
(4) When sampling has been performed for a specific time, the sample & hold circuit enters the hold status, and
(5) Set bit 9 of the successive approximation register (SAR). The tap selector changes the level of the voltage tap
(6) The voltage generated by the voltage tap of the array is compared with the analog input voltage by a
ADAnS registers
The setting of the number of stabilization clocks immediately after A/D conversion is enabled is determined by
the specification of the ADAnM1.ADAnFR0 and ADAnM1.ADAnFR1 bits.
number of stabilization clocks (n = 0, 1). If the ADAnCE bit is set to 1 in the hardware trigger mode (external
trigger mode, timer trigger modes 0, 1), the A/D converter enters the trigger wait status. For details, see 12.3
(2) A/D converter n mode register 1 (ADAnM1) (n = 0, 1).
sample & hold circuit. When the operational amplifier for input level amplification is used, the gain specified by
the OPnCTL0.OPnGA0 bit × the input voltage is sampled.
holds the input analog voltage until A/D conversion ends.
of the array to the reference voltage (1/2 AV
comparator. If the analog input voltage is found to be greater than the reference voltage (1/2 AV
of comparison, the most significant bit (MSB) of the successive approximation register (SAR) remains set. If
the analog input voltage is less than the reference voltage (1/2 AV
input, the conversion result is not correctly stored in the ADAnCRm register and the conversion operation
before the change is initialized and performed from the beginning again (m = 0 to 3).
2. For operation when using the operational amplifier for input level amplification, refer to 12.3
(3) A/D converter n channel specification register (ADAnS) (n = 0, 1).
For the relationship between the analog input pins and A/D conversion result registers, see
Table 12-4.
Note
(n = 0, 1).
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD
DD
).
DD
), the MSB of the SAR is reset.
DD
) as a result
509