M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 66

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

64
(3) On-chip peripheral I/O area
4 KB of memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area.
An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH
Note Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O,
On-chip peripheral I/O registers associated with the operating mode specification and the state monitoring for
the on-chip peripheral I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot
be executed from this area.
Cautions 1. In the V850E/IA3 and V850E/IA4, if a register is word accessed, halfword access is
specify addresses FFFF000H to FFFFFFFH.
After reset: 00H
IMS
2. For registers in which byte access is possible, if halfword access is executed, the higher
3. Addresses that are not defined as registers are reserved for future expansion. If these
performed twice in the order of lower address, then higher address of the word area,
disregarding the lower 2 bits of the address.
8 bits become undefined during the read operation, and the lower 8 bits of data are
written to the register during the write operation.
addresses are accessed, the operation is undefined and not guaranteed.
Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination
address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the
source/destination address of DMA transfer.
IRAM0
0
1
0
6 KB (FFFD800H to FFFEFFFH)
12 KB (FFFC000H to FFFEFFFH)
R/W
Figure 3-9. On-Chip Peripheral I/O Area
0
F F F F F F F H
F F F F 0 0 0 H
CHAPTER 3 CPU FUNCTION
Address: FFFFF9F0H
User’s Manual U16543EJ4V0UD
0
On-chip peripheral I/O area
Specification of internal RAM size
0
(4 KB)
0
0
0
IRAM0
Note
.