M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 52

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
3.2.2
load/store instruction (LDSR or STSR instruction).
50
Register No.
System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, specify a system register number indicated below using the system register
Notes 1.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 by the LDSR instruction, bit 0 will be ignored
Remark
21 to 31
System
6 to 15
16
17
18
19
20
0
1
2
3
4
5
System register set
2.
when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of
the PC is fixed to 0). When setting the value of EIPC, FEPC, and CTPC, use an even value (bit 0 =
0).
√: Access allowed
×: Access prohibited
Because this register has only one set, to enable multiple interrupts, it is necessary to save this register
by program.
Can be accessed only after the DBTRAP instruction or illegal opcode is executed and before the
DBRET instruction is executed.
Status saving register during interrupt (EIPC)
Status saving register during interrupt (EIPSW)
Status saving register during NMI (FEPC)
Status saving register during NMI (FEPSW)
Interrupt source register (ECR)
Program status word (PSW)
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
Status saving register during CALLT execution (CTPC)
Status saving register during CALLT execution (CTPSW)
Status saving register during exception/debug trap (DBPC)
Status saving register during exception/debug trap (DBPSW)
CALLT base pointer (CTBP)
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
System Register Name
Table 3-2. System Register Numbers
CHAPTER 3 CPU FUNCTION
User’s Manual U16543EJ4V0UD
Note 1
Note 1
LDSR Instruction
√
√
Note 2
Note 2
Operand Specification
√
√
√
√
×
√
×
√
√
√
×
STSR Instruction
√
√
Note 2
Note 2
√
√
√
√
√
√
×
√
√
√
×