M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 313

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(c) Notes on rewriting TQnCCR0 register
If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When the overflow may occur, stop counting once and then change the set value.
Note The TOQ10 pin is provided only in the V850E/IA4.
Remarks 1. Interval time (1): (D
If the value of the TQnCCR0 register is changed from D
less than D
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
overflows, and then counts up again from 0000H. When the count value matches D
signal is generated and the output of the TOQn0 pin is inverted (the TOQ10 pin is provided only in the
V850E/IA4).
Therefore, the INTTQnCC0 signal may not be generated at the interval time “(D
or “(D
+ 1) × Count clock cycle”.
TOQn0 pin
2
INTTQnCC0 signal
TQnCCR0 register
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
16-bit counter
2. n = 0, 1
1
, the count value is transferred to the CCR0 buffer register as soon as the TQnCCR0 register
TQnOL0 bit
TQnCE bit
Interval time (NG): (10000H + D
Interval time (2): (D
Note
FFFFH
0000H
output
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
L
Interval time (1)
1
2
User’s Manual U16543EJ4V0UD
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
D
1
2
+ 1) × Count clock cycle
D
2
2
Interval time (NG)
, however, the 16-bit counter counts up to FFFFH,
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
Interval
time (2)
D
2
1
+ 1) × Count clock cycle”
2
2
.
, the INTTQnCC0
2
311
but
2

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