ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 105
ATTINY43U-MU
Manufacturer Part Number
ATTINY43U-MU
Description
MCU AVR 4K FLASH 8MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY43U-MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 105 of 182
- Download datasheet (4Mb)
8048B–AVR–03/09
Figure 14-4. Two-wire Mode Operation, Simplified Diagram
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
Figure 14-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
1. The start condition is generated by the master by forcing the SDA low line while keep-
SDA
SCL
SLAVE
MASTER
ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the
USI Data Register, or by setting the corresponding bit in the PORTA register to zero.
Note that the Data Direction Register bit must be set to one for the output to be
enabled. The start detector logic of the slave device (see
Bit7
Bit7
Bit6
Bit6
S
A B
Bit5
Bit5
C
ADDRESS
Bit4
Bit4
1 - 7
Bit3
Bit3
R/W
Bit2
Bit2
(Figure
8
D
Bit1
Bit1
14-5), a bus transfer involves the following steps:
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
ACK
Control Unit
9
Figure 14-6 on page
PORTxn
DATA
1 - 8
HOLD
SCL
SDA
SCL
SDA
SCL
ACK
9
106)
F
P
VCC
105
Related parts for ATTINY43U-MU
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
Microcontrollers (MCU) 512B FL 32B SRAM TIMER ATTINY4 12MHz
Manufacturer:
Atmel
Part Number:
Description:
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet: