ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 12

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.1
4.7
12
Instruction Execution Timing
ATtiny43U
SPH and SPL — Stack Pointer Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-4 on page 12
by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 4-4.
Figure 4-5 on page 12
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 4-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Read/Write
Initial Value
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
RAMEND
RAMEND
SP15
R/W
R/W
SP7
15
7
clk
clk
CPU
shows the parallel instruction fetches and instruction executions enabled
CPU
shows the internal timing concept for the Register File. In a single clock
RAMEND
RAMEND
SP14
SP6
R/W
R/W
14
6
RAMEND
RAMEND
SP13
SP5
R/W
R/W
CPU
13
5
T1
T1
, directly generated from the selected clock source for the
RAMEND
RAMEND
SP12
R/W
R/W
SP4
12
4
RAMEND
RAMEND
T2
SP11
SP3
R/W
R/W
T2
11
3
RAMEND
RAMEND
SP10
SP2
R/W
R/W
10
2
T3
T3
RAMEND
RAMEND
R/W
R/W
SP9
SP1
9
1
RAMEND
RAMEND
SP8
SP0
R/W
R/W
8
0
8048B–AVR–03/09
T4
T4
SPH
SPL