ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 59

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3
10.3.1
8048B–AVR–03/09
Register Description
MCUCR – MCU Control Register
Figure 10-1. Timing of pin change interrupts
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
External Interrupt 0 is activated by the external pin INT0 if the I-flag of SREG and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
Edges on INT0 are registered asynchronously. Pulses on INT0 wider than the pulse width given
in
erate an interrupt.
Bit
0x35 (0x55)
Read/Write
Initial Value
pcint_setflag
pcint_in_(0)
Table 20-6 on page 158
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
BODS
LE
R/W
7
0
pin_lat
Table 10-2 on page
D
PUD
Q
R/W
6
0
pin_sync
will generate an interrupt. Shorter pulses are not guaranteed to gen-
PCINT(0) in PCMSK(x)
R/W
SE
5
0
pcint_in_(0)
SM1
R/W
60.
4
0
0
x
clk
SM0
R/W
3
0
pcint_syn
BODSE
R/W
2
0
pcint_setflag
ISC01
R/W
1
0
ISC00
R/W
PCIF
0
0
MCUCR
59