ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 32

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.2
7.1.3
7.2
7.3
32
Software BOD Disable
Power Reduction Register
ATtiny43U
ADC Noise Reduction Mode
Power-Down Mode
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the
Comparator Control and Status Register” on page
Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the
Watchdog to continue operating (if enabled). This sleep mode halts clk
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-
dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out
Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This
sleep mode halts all generated clocks, allowing operation of asynchronous modules only.
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see
140), the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible for software to disable the BOD in Power-Down Mode (see
Mode” on page
BOD is globally disabled by fuses. If disabled by software, the BOD is turned off immediately
after entering the sleep mode and automatically turned on upon wake-up. This ensures safe
operation in case the V
When the BOD has been disabled the wake-up time from sleep mode will be the same as the
wake-up time from RESET. This is in order to ensure the BOD is working correctly before the
MCU continues executing code.
BOD disable is controlled by bit 7 (BODS — BOD Sleep) of MCU Control Register, see
– MCU Control Register” on page
Mode, while a zero in this bit keeps BOD active. The default setting is zero, i.e. BOD active.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
The Power Reduction Register (PRR), see
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozenand the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
32). The sleep mode power consumption will then be at the same level as when
CC
level has dropped during the sleep period.
34.
34. Writing this bit to one turns off the BOD in Power-Down
“PRR – Power Reduction Register” on page
113. This will reduce power consumption in
I/O
, clk
Table 19.2 on page
CPU
“ACSR – Analog
, and clk
“Power-Down
8048B–AVR–03/09
“MCUCR –
“MCUCR
35, pro-
FLASH
,