ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 96

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.9.12
12.9.13
12.9.14
96
ATtiny43U
TIMSK1 – Timer/Counter 1 Interrupt Mask Register
TIFR0 – Timer/Counter 0 Interrupt Flag Register
TIFR1 – Timer/Counter 1 Interrupt Flag Register
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCIEnB: Timer/Countern Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Countern occurs, i.e., when the OCFnB bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFRn.
• Bit 1 – OCIEnA: Timer/Countern Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Countern Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Countern occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
• Bit 0 – TOIEn: Timer/Countern Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-
tern Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Countern occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-
ister – TIFRn.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCFnB: Output Compare Flag n B
The OCFnB bit is set when a Compare Match occurs between the Timer/Countern and the data
in OCRnB – Output Compare Registern B. OCFnB is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable),
and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed.
Bit
0x0C (0x2C)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
Bit
0x0B (0x2B)
Read/Write
Initial Value
R
7
–
0
R
R
7
–
0
7
–
0
R
6
–
0
R
R
6
–
0
6
–
0
R
5
–
0
5
–
R
0
5
–
R
0
R
4
–
0
R
R
4
–
0
4
–
0
R
3
–
0
R
R
3
–
0
3
–
0
OCIE1B
OCF0B
OCF1B
R/W
R/W
R/W
2
0
2
0
2
0
OCIE1A
OCF0A
OCF1A
R/W
R/W
R/W
1
0
1
0
1
0
TOIE1
TOV0
TOV1
R/W
R/W
R/W
0
0
0
0
0
0
8048B–AVR–03/09
TIMSK1
TIFR0
TIFR1