ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 90

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.9
12.9.1
12.9.2
90
Register Description
ATtiny43U
TCCR0A – Timer/Counter Control Register A
TCCR1A – Timer/Counter Control Register A
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bits 7:6 – COMnA[1:0]: Compare Match Output A Mode
These bits control the Output Compare pin (OCnA) behavior. If one or both of the COMnA[1:0]
bits are set, the OCnA output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA pin
must be set in order to enable the output driver.
When OCnA is connected to the pin, the function of the COMnA[1:0] bits depends on the
WGMn[2:0] bit setting.
WGMn[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 12-2.
TCNTn
(clk
(CTC)
OCRnx
Bit
0x30 (0x50)
Read/Write
Initial Value
Bit
0x2F (0x4F)
Read/Write
Initial Value
OCFnx
clk
clk
COMnA1
I/O
I/O
Tn
/8)
0
0
1
1
caler (f
Compare Output Mode, non-PWM Mode
COM0A1
COM1A1
R/W
R/W
COMnA0
7
0
7
0
0
1
0
1
clk_I/O
TOP - 1
Table 12-2 on page 90
COM0A0
COM1A0
R/W
R/W
/8)
6
0
6
0
Description
Normal port operation, OCnA disconnected.
Toggle OCnA on Compare Match
Clear OCnA on Compare Match
Set OCnA on Compare Match
COM0B1
COM1B1
R/W
R/W
5
0
5
0
COM0B0
COM1B0
TOP
R/W
R/W
4
0
4
0
shows the COMnA[1:0] bit functionality when the
TOP
R
R
3
0
3
0
–
–
BOTTOM
R
R
2
0
2
0
–
–
WGM01
WGM11
R/W
R/W
1
0
1
0
WGM00
WGM10
R/W
R/W
BOTTOM + 1
0
0
0
0
8048B–AVR–03/09
TCCR0A
TCCR1A