ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 91

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8048B–AVR–03/09
Table 12-3 on page 91
to fast PWM mode.
Table 12-3.
Note:
Table 12-4 on page 91
to phase correct PWM mode.
Table 12-4.
Note:
• Bits 5:4 – COMnB[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OCnB) behavior. If one or both of the COMnB1:0
bits are set, the OCnB output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnB pin
must be set in order to enable the output driver.
When OCnB is connected to the pin, the function of the COMnB[1:0] bits depends on the
WGMn[2:0] bit setting.
WGMn[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 12-5.
COMnA1
COMnA1
COMnB1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnA equals TOP and COMnA1 is set. In this case, the Com-
1. A special case occurs when OCRnA equals TOP and COMnA1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
for more details.
pare Match is ignored, but the set or clear is done at TOP. See
page 87
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
Compare Output Mode, non-PWM Mode
COMnA0
COMnA0
COMnB0
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Table 12-5 on page 91
shows the COMnA[1:0] bit functionality when the WGMn[1:0] bits are set
shows the COMnA[1:0] bit functionality when the WGMn[2:0] bits are set
Description
Normal port operation, OCnA disconnected.
WGMn2 = 0: Normal Port Operation, OCnA Disconnected.
WGMn2 = 1: Toggle OCnA on Compare Match.
Clear OCnA on Compare Match, set OCnA at TOP
Set OCnA on Compare Match, clear OCnA at TOP
Description
Normal port operation, OCnA disconnected.
WGMn2 = 0: Normal Port Operation, OCnA Disconnected.
WGMn2 = 1: Toggle OCnA on Compare Match.
Clear OCnA on Compare Match when up-counting. Set OCnA on
Compare Match when down-counting.
Set OCnA on Compare Match when up-counting. Clear OCnA on
Compare Match when down-counting.
Description
Normal port operation, OCnB disconnected.
Toggle OCnB on Compare Match
Clear OCnB on Compare Match
Set OCnB on Compare Match
shows the COMnB[1:0] bit functionality when the
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on page 85
91