ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 92

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

92
ATtiny43U
Table 12-6 on page 92
to fast PWM mode.
Table 12-6.
Note:
Table 12-7
rect PWM mode.
Table 12-7.
Note:
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – WGMn[1:0]: Waveform Generation Mode
Combined with the WGMn2 bit found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode,
and two types of Pulse Width Modulation (PWM) modes (see
COMnB1
COMnB1
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnB equals TOP and COMnB1 is set. In this case, the Com-
1. A special case occurs when OCRnB equals TOP and COMnB1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
for more details.
shows the COMnB[1:0] bit functionality when the WGMn2:0 bits are set to phase cor-
pare Match is ignored, but the set or clear is done at TOP. See
page 87
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COMnB0
COMnB0
for more details.
0
1
0
1
0
1
0
1
shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set
Description
Normal port operation, OCnB disconnected.
Reserved
Clear OCnB on Compare Match, set OC0B at TOP
Set OCnB on Compare Match, clear OC0B at TOP
Description
Normal port operation, OCnB disconnected.
Reserved
Clear OCnB on Compare Match when up-counting. Set OCnB on
Compare Match when down-counting.
Set OCnB on Compare Match when up-counting. Clear OCnB on
Compare Match when down-counting.
Table 12-8 on page
93. Modes of operation supported by the
(1)
“Modes of Operation” on page
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on page 85
8048B–AVR–03/09
84).